INTRODUCTION


       This manual describes the logical structure and operation of the
English Electric DEUCE Computer. This is a high-speed general-purpose
electronic digital computer.
       The individual circuits and other parts of the DEUCE are described
only in terms of their functions and of the sequence of signals passing
between them. Only indirect and occasional reference is made to the
operation of the electronic circuits as such.
       The reader is assumed to be familiar with the notation of repres-
enting positive and negative binary numbers within the computer. Reference
is made to the section of the DEUCE Programming Manual describing this
notation.
       Modified or additional sections of this manual will be issued from
time to time to keep it up to date with the continuing programme of
improvements to the facilities and operation of the computer.

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                                 INDEX


CHAPTER                          TITLE                          PAGE


   1                  Brief General Description                   1

   2                  Main Component Parts                       12

   3                  Logical Diagrams                           14

   4                  Fundamental Waveforms                      19

   5                  The Circulation Unit                       23

   6                  Control                                    26

   7                  Destination Triggers                       47

   8                  Logical Operations Unit                    49

   9                  The Adder                                  51

  10                  The Multiplier-Divider Unit                55

  11                  The Magnetic Store                         87

  12                  The Reader and Punch                       98

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BRIEF GENERAL DESCRIPTION

The operation Of the DEUCE will first be described as a whole, with reference to most of its essential parts, before each part is described in detail. In this rapid preliminary survey, a number of difficulties will necessarily be glossed over, it is thought worth while, however, to give the reader as quickly as possible a general framework into which subsequent details can be fitted. REPRESENTATION OF NUMBERS AND INSTRUCTIONS Within the computer a number is represented, in binary form, by a sequence of electric pulses, at intervals of 1 microsec, occupying 32 microsec in all. There are in general less than 32 pulses, since each pulse represents a digit "1" in the number and a digit "0" is denoted by a vacant microsec In which no pulse occurs. The least significant digit always comes first. Thus the number "13"; would be represented in 32 microsec at any point in the Machine by a pulse in the first, third and fourth microsec and the absence of pulses in the second, fifth and subsequent microsec. The significance of the three pulses present is respectively 20 = 1, 22 = 4 and 23 = 8. The same type of signal, consisting of 32 pulses and spaces at 1 microsec intervals, is also used to represent an instruction. This means that the same storage mechanism can be used for either numbers or instructions, and that an instruction can be modified, if required, by the normal arithmetic units. For this reason, a common name is required for any sequence of 32 digits which may be either a number or an instruc- tion; the name chosen for this purpose is "word". DELAY LINE STORAGE The main type of storage unit is founded on a delay element which after a constant delay reproduces at its output terminal any, signal applied to its input terminal. In the simplest case, the delay is 32 microsec. Such an element is shown in Figure 1.1 with switches for input and output. Suppose that switch D is opened to connect the input with the delay, a single pulse is applied to the input and enters the delay, and switch D is immediately closed. The pulse will travel along the delay, emerge at B 32, microsec later and immediately return to point A via switch D. It will then retraverse the delay and appear at B after a further 32 microsec. This process is repeated indefinitely, provided switch D is not disturbed; a single pulse appears regularly at B, once every 32 microsec. In effect, a word has been stored which consists of NS-y-37/11-57

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a single "1" and 31 zeros. Any other pattern could equally well have been stored, since the successive digits would follow each other through the delay and emerge in their proper order. To store a particular word, its successive digits are applied at the input, switch D in opened and the digits flow into the delay; after 32 microsecs the last digit has just entered the delay and the first is about to emerge; at this moment, switch D is closed to complete the circulation path. The successive digits as they emerge at B are transmitted back to A and re-enter the delay; no more digits are accepted from the input. Any word previously stored in the system has now been lost, since the circulation path was broken during the process of introducing the new one. A copy of the word currently being stored may at any time be obtained at the output simply by operating switch S. Switch D is known as the "Destination Gate", switch S as the "Source Gate". MINOR CYCLES It will be observed that the word is stored like a whiting; it appears repeatedly at point B, its last digit always being immediately followed by its first. There is thus no indication in the stored digits of where the word begins and ends. The Operation of the DEUCE is con- trolled by a sequence of short pulses which occur incessantly at intervals of 32 microsec; every operation begins at one of these pulses and ends at another. The period of 32 microsec between two successive control pulses is called a "minor cycle" (abbreviated "m.c.") The 32 digits of a word which are applied to A during one minor cycle, appear at B during the next; thus a control pulse always marks the moment when one word has just ended and the next (or a repeat of the same one) is about to begin. LONGER DELAY LINES In the same way that 32 digits are stored in a delay element of 32 microsec, 1024 digits may be stored in a delay element of 1024 microsec. These 1024 digits are generally regarded as making up 32 words of 32 digits each; this longer delay thus provides 32 storage positions for single words. These words appear in rotation at the output in succes- sive minor cycles; to keep track of them the minor cycles are numbered from 0 to 31 and then starting again at 0. A sequence of 32 minor cycles is called a "Major Cycle". It is clear that a word which emerges from the delay in minor cycle 5 of some Major Cycle will reappear in m.c. 5 of the next and every subsequent Major Cycle until it is replaced with another word. The word is said to be stored in m.c. 5 (of this Delay Line). To replace this word with a new one without affecting the contents of any other minor cycle. the Destination Gate must be opened only during m.c. 5; also, the new word to be stored must he presented at the input during this minor cycle, whether or not it is repeated in the previous and succeeding minor cycles. For every minor cycle in which the Destination Gate is open, the word previously stored will be replaced by NS-y-37/11-57

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the word then being applied to the input. The timing of the Destination Gate must therefore be closely controlled; a special signal is supplied for this purpose. It will be seen, however, that the timing requirement for the Source Gate is far less stringent. LAYOUT OF DELAY LINE STORE The DEUCE storage system includes twelve of these 1024 microsec delay lines, four of 32 microsec each and also three of 64 microsec for two words each and two of 128 microsec for four words each. The delay lines are numbered from 0 to 21, and each number is prefixed by a two- letter code which indicates the storage capacity. The complete layout is as follows: Delay Words Stored Name Number References 1024 microsec 32 each "Delay Line" 12 DL1 to DL12 32 microsec 1 each "Temporary Store" 4 TS13 to TS16 128 microsec 4 each "Quadruple Store" 2 QS17 and QS18 64 microsec 2 each "Double Store" 3 DS19,DS20,DS21 NOTATION FOR QS AND DS STORAGE The four words in a QS are said to be stored in minor cycles 0, 1, 2 and 3. though the word in m.c. 3, for instance, emerges not only in m.c.3 but in m.c. 7, 11, 15 ... 27 and 31. It may be used or replaced in any of these minor cycles. The word emerging from QS 17 in m.c. 3 is said to be stored in 173; this notation is used for all DL, QS and DS, though the range of numbers appearing as the suffix is different in the three cases. The two minor cycles of a DS are numbered "2" and "3" rather than "0" and "1"; this is to avoid confusion with the "0" meaning "odd minor cycle". Comparing a DL with a TS it will be seen that the DL has the advan- tage of storing 32 times as much information with very little extra equipment; on the other hand, a given one of the 32 words stored is available for use or replacement only once in a Major Cycle instead of in every minor cycle. By using a range of TS, DS, QS and DL it is intended to have the best of both worlds, very rapid access to the words in imme- diate use combined with economy of storage equipment. This principle will be discussed further when we come to consider the Magnetic Store and its relation with the Delay Line store. INTERCONNECTIONS IN THE DELAY LINE STORE Figure 1.2 shows DL1, DL2, TS13 and TS14, with their common connec- tions. The common connection of all Input and Output points is called the Highway. The process will be described of transferring a word from one position to another within this elementary store. It will not yet NS-y-37/11-57

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be clear why this procedure is in any way useful, but we will let that pass for the moment. To replace the word in TS13 with a copy of that in TS14, the first thing is to open S14; repeated copies of the word in TS14 flow through the Highway and appear at all the Destination Gates. D13 is now opened; the word on Highway flows into TS13, while the old word in TS13 is lost, digit by digit, as it emerges from the delay. After 32 microsec (or more, it does not matter in this case) D13 is closed, trapping the word from TS14 in TS13. The Computer is now free to proceed to its next operation. This might be to replace the word in 27 with a copy of that in 14. The procedure is the same, except that in this case it is essential for D2 to be opened sharply at the beginning of m.c. 7 and closed equally suddenly at the end. Otherwise, more than one word in DL2 will be replaced with copies of the one in TS14. To replace the word in 27 with a copy at that in 17, S1 may be opened at any time; it is again essential for D2 to be opened only during m.c. 7. A direct transfer is impossible from, say, 112 to 27; this process can be effected only in two stages, transferring first from 112 to any idle TS and then from there to 2. Similarly, direct transfers cannot take place from (DS) 192 to (DS) 213 , to (QS) 171, or to any odd minor cycle in a DL, or from (QS) 183 to 192, to 171,or to any minor cycle of a DL other than m.c. 3, 7, 11, 15, 19, 23, 27 or 31. Incidentally, transfers are possible which last for any integral number of minor cycles up to 32. This timing, of course, refers to the opening of the Destination Gate for the relevant period; the Source Gate is always opened for a period which overlaps this at both ends. For instance, one may in one operation replace the words in DL1 m.c. 21 to 24 either with four copies of the word in TS16, with two copies each of the two words in DS20, with one copy each of the four words in QS18 or with the four words in DL2 m.c. 21 to 24. OTHER SOURCES AND DESTINATIONS The DEUCE works by carrying out a sequence of transfers in a pre- Determined order. For each transfer, the Source and Destination numbers must be specified, as well as the minor cycle or sequence of minor cycles for which Transfer is to take place. There are 32 Sources and 32 Destinations, each numbered from 0 to 31. 21 Sources and 21 Destinations are associated with the different storage positions. The other 11 of each are connected to various pieces of equipment for doing arithmetic operations and controlling the input and output devices. In these cases, there is no particular relationship between the Source and Destination bearing the same number. NS-y-37/11-57

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In the usual abbreviation, a transfer from S14 to D13 for example is Written "14-13". Where a DL is involved, the minor cycles of operation Must also be specified as in "4-7 (m.c. 14, 15 and 16)". In some cases, only the number of m.c. is relevant; "18-17 (4 m.c.)" replaces all four words in QS17 with copies of those on QS18; this is not affected by which four minor cycles are used for the transfer, and it could, in fact, go on for more than four minor cycles without further effect. INSTRUCTIONS Each transfer is specified by an "Instruction"; this is a word of 32 digits coded in a special way to represent the required transfer. The precise form of coding will be described later; it will suffice for the moment to say that any of the transfers mentioned as examples are capable of being represented by an Instruction within this code. CONTROL MECHANISM There is a part of the DEUCE called "Control" whose function is to interpret Instructions from the coded form and make the necessary connections for them to be obeyed. Instructions to be obeyed are nor- mally stored in the Delay Line store; the Control incorporates a special storage line, TS COUNT, in which is held the Instruction currently being obeyed. The pattern of operation is to take an Instruction into TS COUNT, set up the necessary connections and obey it, and then take in the next Instruction. Since the computation performed is determined as much by the sequence in which Instructions are obeyed as by the individual Instruc- tions themselves, it is arranged for each Instruction to specify, as well as the Source. Destination and minor cycle or cycles of transfer, the storage location of its successor. INSTRUCTION HIGHWAY There are two entrances by which a word may reach Control to be obeyed as an Instruction. The usual one is available only to words stored in one of the first eight DLs (DL1 to DL8 inclusive), a maximum total of 256 words. Each of these DLs has, as well as its Scores and Destination Gates, an extra gate called its "Next Instruction Source Gate". These are numbered from 0 to 7, numbers 1 to 7 referring to the corresponding DL and number 0 referring to DL8. These eight "NIS" Gates lead, not on to the main Highway, but on to a special "Instruction High- way" (IHW) which leads in turn to Control. The connections for DLs 1, 2 and 8 are shown in Figure 1.3. By opening only the NIS Gate specified in the current Instruction, Control ensures that the next Instruction will come from the required DL. There remains the timing problem of picking out from IHW the correct one of the 32 words in that DL. This is solved by admitting the IHW signal into TS COUNT through a special gate which is opened only for the minor cycle in which the required new Instruction word is emerging from its DL of residence. NS-y-37/11-57

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The second entrance to Control is described in the next paragraph but one. TIMING SIGNALS Control is thus required to generate two timing signals. One opens the selected Destination Gate and thus controls the main Transfer Timing; this signal is called Transtim or TT. The other opens the gate into TS COUNT and thus controls the Timing at which Control takes in the new Instruction; it is called Timci or TCI. The only other signals emerging from Control are the three sets of Selection signals, one set each for Source, Destination and Next Instruc- tion Source. DESTINATION "0" The other entrance to Control is through a special Destination Gate which has been given the number "0". Operation of this gate usurps the IHW connection to TS COUNT and replaces it with a connection from the main Highway. Thus by this means it is possible to inject into TS COUNT as an Instruction any word which is available at a Source. For instance, the Instruction "13-0" takes as its next Instruction the word currently stored in TS13. The connections are shown in Figure 1.4. It will be seen that a word from HW transferred to D0 has still to pass through the TCI gate; this means that both TCI and TT signals must be present simultaneously for the Instruction to take effect. DISCRIMINATION It frequently occurs in the course of a computation that what is to be done next depends on what has already happened. Reduced to its essentials this requires the existence of an Instruction which is capable of being followed by either of two successors depending, in some sense, on "circumstances". This requirement is met by two special Destinations D27 and D28. An Instruction which transfers a number to one of these Destinations picks its succeeding Instruction word from either of two Locations (in practice, adjacent minor cycles of the same DL) depending on some characteristic of the number transferred. D27 discriminates between positive and negative numbers, D28 between zero and non-zero numbers. For example, which of two possible Instructions comes next after "13-27" depends on the sign of the number in TS13. D27 and D28 work by modifying the TCI Gate timing signal, and therefore form part of Control. Figure 1.5 shows the Control as a block with all its input and output connections. ARITHMETIC OPERATIONS An essential function of a Computer is to carry out some selection NS-y-37/11-57

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of arithmetic operations. In the DEUCE, this is achieved with the same "transfer" type of operation by giving special facilities to certain of the Sources and Destinations. Each of these arithmetic Sources and Destinations is associated with a particular TS or DS (sometimes with two, as in the case of multiplication where a TS is used to store the multiplicand and a DS holds the multiplier at the beginning and the double-length product at the end of the operation. But this is compli- cated - we will start with a simpler example). ADDITION Addition may be performed by using D25, which is associated with TS13. The arrangement is shown in Figure 1.6. The function of the box Marked "+" is to add together the two numbers applied at the input Terminals A and B and to present the sum of the two at the output terminal C. It will be appreciated that the two sequences of pulses and spaces at A and B may be taken to represent two binary numbers, that these two binary numbers have a unique binary sum, and that this binary sum can in turn be uniquely expressed as a sequence of pulses and spaces. This is the output signal produced by the "+" box or "Adder". If D25 is not being used, the signal at A always represents the number zero; the signals at C and B are then identical and TS13 acts as a simple storage position for all purposes, the Adder appearing as a short- circuit between B and C. When a transfer is made to D25, the number or numbers transferred are added to the previous contents of TS13. A few examples of such transfers will be given. "14-25" replaces the number in TS13 with the sum of those previously in TS13 and TS14 (TS14, of course, remains unchanged). "14-25 (3 m.c.)" adds three times the number in TS14 to that previously in TS13. "13-25" doubles the number in TS13 or, to put it another way, shifts the number in TS13 up by one binary place. "13-25 (5 m.c.)" gives a shift up of five binary places. "1-25 (32 m.c.)" adds the 32 numbers in DL1 together into TS13. It will be observed that D25 and D13 cannot both be used at once; an Instruction contains only one Destination number. ARITHMETIC SOURCES Several Source numbers are allocated to arithmetic operations. As in the case of arithmetic Destinations, only one example will be given at the moment. We have seen how to shift a number upwards by putting it in TS13 and using D25. A number may be shifted downwards by putting it in TS14 and using S23. The connections are shown in Figure 1.7. The box "L" has one input at A and two outputs at B and C. That at B is identical with the input, that at C represents the input number divided by two, that is shifted down by one binary place. The Instruction "23-14 (6 m.c.)" has the effect of shifting the number in TS14 down by six binary places. NS-y-37/11-57

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FIXED NUMBERS Certain useful fixed binary configurations are permanently available At Sources. These include "all zeros" at S30, "all ones" at S31 and at S27 a configuration containing a single "1" in the least significant position. This last in called "P1". The Instruction "27-25" adds one to the number in TS13. The method of generating P1 will be described later; for the present the notation of Figure 1.8 will be used. INPUT AND OUTPUT Numbers and Instructions reach the Machine from outside by being injected on to Highway through Source 0. In the course of a computation, the Computer assimilates new information when required (either more data or further Instructions) by obeying an Instruction with Source number "0", which has been included in the program. To get started in the first place, a key is pressed which clears the whole Delay Line Store; this leaves to be obeyed the Instruction "0-0", which has the effect of reading a single (Instruction) word from the Input to TS COUNT. This single spy is used to call in a platoon, a company and finally the big battalions. Calculated results are sent out from Highway through D29. A schematic of SO and D29 is given in Figure 1.9 for the sake of complete- ness rather than explanation. Input and Output, by the way, is always in signal notes. The Instruction "0-4 (m.c. 7)" sends the word currently at the Input to 47; "14-29" sends the word in TS14 to the output. These few notes on Input and Output have no doubt raised more questions than they have answered; these will be dealt with, it is hoped, in later sections of this report. DESTINATION "TRIGGERS" All the operations so far described have had some genuine element of "transfer" in the sense that digits flowed from one part of the Machine to another. There remain some cases, however, in which this is not true. The problem is to fit these into the "Source and Destination" framework so that the same form of Instruction word can be used. One special Destination is therefore allotted jointly to all these operations which lack the "transfer" element; this is D24, called "Destination Triggers". There are about a dozen of these operations altogether, each of which is specified by a particular Source number used in conjunction with D24; a few examples will be given. Information normally comes into the DEUCE punched on Hollerith cards which pass successively through a Reading machine in response to a demand from the Computer. This demand is the Instruction "12-24" which causes a sequence of cards to start passing through the Reader; the flow may be stopped at any time by the Instruction "9-24". Output of information NS-y-37/11-57

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is through a Punching machine which is fed with a supply of clean cards; the Punch in started by "10-24" and stopped by "9-24". The same Instruction is used to stop either the Reader or the Punch because they are never in practice used at the same time. The DEUCE contains an automatic Multiplier and an automatic Divider; operation of these is initiated respectively by "0-24" and "1-24". In these cases there is no corresponding stopping Instruction, since both circuits are arranged to stop themselves automatically as soon as the arithmetic operation is complete. Figure 1.10 shows the D24 connections. It will be seen that there is no concoction with Highway; this permits the dual function of the Source selector. Obeying an Instruction with Source number 12, for example, means both that the contents of DL12 will appear on Highway and that if the Destination number is 24 the Reader will be started; in the latter case, the contents of Highway is irrelevant, since none of the Destination gates connected to it is open. The two "switches" labelled "S12", for example; one connected to Highway and one to Destination Triggers; actually represent two separate electronic gating circuits operated by the same control signal. THE MULTIPLIER The operations of multiplication and division are somewhat different from the arithmetic operations so far described. Only the Multiplier operation will be described at present, since that of the Divider is similar. A Multiplication requires several Instructions; first the two factors must be sent to particular storage positions, the multiplicand to TS16 and the multiplier to DS213. Next, DS212 must be cleared. Now we are ready. The Multiplier is brought into action by obeying the Instruction "0-24", which uses Destination Triggers. After 65 minor cycles, multiplication is complete, and the product, which comprises 64 digits, remains in DS21. The multiplier has been lost but the multipli- cand remains in TS16. The Multiplying circuit automatically switches itself off 65 m.c. after the start. Figure 1.11 shows a schematic of the system. MAGNETIC STORE As well as the Delay Line Store, the DEUCE has an auxiliary store, called the Magnetic Store, for about 8000 words. This is much larger than the Delay Line Store, but the information takes a longer time to get into and out of it. The Magnetic Store works by taking information from the Delay Line Store, holding it, and returning it later when it is wanted. Information is transferred in either direction, always in blocks of 32 words, and always to or from DL11. In other words, the two operations NS-y-37/11-57

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in which the Magnetic Store is concerned are to transfer the whole contents of DL11 into the Magnetics and to transfer a clock of 32 words from the Magnetics into DL11. Two special Destinations, D30 and D31 are allocated the job of initiating these "Magnetic Transfers". Figure 1.12 shows the system, only one Magnetic Control Destination, i.e. D30, being shown. MAIN SCHEMATIC OF THE DEUCE We are now in a position to assemble the various components so far Described into a coherent whole. Figure 1.13 is a schematic of the whole machine. For the sake of simplicity, only one or two examples have been included from each group of parts of a similar type; for example, from the group of five Sources S27(P1), S23(P17), S29(P32), S30(Zeros) and S31(Ones), only the first is explicitly shown in the figure. We will trace through the successive operations of "obeying an Instruction". Suppose the Instruction enters TS COUNT in minor cycle "m". In m.c. (m+1) it first enters the main part of Control and the three selectors are set up; nothing else happens in this minor cycle, which is therefore known as the "set-up" minor cycle. The Source and NIS selection take immediate effect, in the sense that digits from the selected Source immediately begin to flow into Highway and that digits from the selected NIS immediately begin to flow Into IHW. The Destination selection does not take effect until Transtim signal is supplied. The transfer specified by the Instruction may commence with any minor cycle from (m+2) to (m+33) and may continue for any integral number of minor cycles from 1 to 32. Thus after the set-up minor cycle there is a pause of from 0 to 31 m.c. as specified in the Instruction; then Transtim signal is applied for a period of from 1 to 32 m.c. and "transfer" takes place for this period. This "transfer" may be a simple transfer of words between sections of the Delay Line Store; it may be an addition in TS13 or a shift in TS14, it may be the initiation of a multiplication or division, of a passage of cards through the Reader or Punch, or of a Magnetic Transfer; it may be the transfer of a word from the input or to the output; it may be the insertion of a number into the Discrimination circuits to determine, according to its sign, the selection of the next Instruction; it may be the direct insertion into TS COUNT of a word which has been built up in a TS by arithmetic action and is now required to be obeyed as an Instruction. Which, of all these, is determined by the particular Source and Destination numbers speci- fied in the instruction. For all this time, the successive words in the DL whose NIS has been Selected have been flowing into IHW and presenting themselves in turn at the TCI gate into TS COUNT. Once the transfer has been completed and Transtim removed, TCI signal is supplied for that single minor cycle in which the required next Instruction emerges from this D.L. Thus the next NS-y-37/11-57

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Instruction gets into TS COUNT and the cycle of operation begins again. Since the new Instruction passes once through TS COUNT before it reaches the main part of Control to take effect, it may actually be admitted to TS COUNT during the last minor cycle of Transtim, though never, of course, any earlier. This enables a minor cycle to be saved in the operation time of a large number of Instructions, and is essential in any transfer to D0. NS-y-37/1<1-57

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MAIN COMPONENT PARTS

In physical form, the DEUCE may be said to consist of six main parts Joined together by electrical connections, though two of them are also joined together physically. They are the Main Frame, the Control Panel, the Reader, the Punch, the Delay Line Store and the Power Unit. READER AND PUNCH The main input and output of information, including the input of the Program, is by Hollerith cards. The DEUCE must therefore incorporate devices for reading and punching these cards. In each case, a standard piece of Hollerith machinery has been modified by replacing its electric circuits with relay mechanisms which link its operation with that of the Computer. The Reader is made from a Balancing Tabulator, the Punch from a Gang Punch. Both are joined with the rest of the DEUCE by cables. MAIN FRAME The electronic circuits comprise about 1450 valves with their Associated components. These are mounted in about 68 chassis each of which has 20 or 30 valves. A chassis consists of a more or less flat plate with the valves sticking out on one side and the components mounted on the other. The individual chassis are mounted in a Main Frame which consists of nine vertical racks solidly mounted together, each capable of holding eight chassis. Each chassis is a self-contained unit, connected to the Main Frame by a pair of plugs and held in place by two bolts. One of the plugs carries the power supplies which are in a standard arrangement for all chassis; the other carries the signal connections between chassis. Most chassis are individual and not like any other, but there are a few groups of identical chassis. For instance, the gates and some of the amplifiers associated with a delay line storage position are made up into a standard chassis called a Circulation Unit. There are, of course, 22 copies of this chassis in the machine, one for each storage location including TS COUNT. The Magnetic Storage Drum is also mounted in the Main Frame on a special chassis not of the standard shape. POWER UNIT The Power Unit takes in a three-phase mains supply and produces all the d.c. and a.c. voltages required by the rest of the DEUCE. There are NS-y-37/11-57

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seven d.c. lines to the Main Frame, -300v, -200v, -100v, earth, +100v, +200v and +300v. Special d. c. supplies are also required for the Reader and Punch and for the relays in the Control Panel. Valve heater supplies are generated by transformers mounted on the Main Frame fed with a.c. mains voltage from the Power Unit. The mains switching is done by contactors operated with buttons; a duplicate set of buttons is mounted on the Control Panel. DELAY LINE STORE The twelve long delay lines of 1024 microsec each are mounted in a Small thermostatic chamber connected by cables to the Main Frame. Above the periphery of the upper part of the chamber are mounted a pair of amplifiers to each DL, one power amplifier for the input signal, one high gain amplifier for the output signal. The complete unit is capped by an overhanging lid giving the appearance of a mushroom. CONTROL PANEL The Control Panel, which is mounted on the main frame, carries a Multiplicity of keys, buttons, lamps and monitors which are not used much when the DEUCE is working normally on computation. The Control Panel comes into its own in investigating faults in the operation of the Computer and when testing and correcting the operation of a new program. The Control Panel carries a row of 32 keys for the input of single numbers and a row of 32 lamps for the output of single numbers, an alarum buzzer and lamp to indicate the failure of an internal check in the program, two monitor cathode-ray tubes for displaying the contents of the various delay line storage positions, and keys for imitating almost everything that the DEUCE normally does automatically. For instance, there is a key labelled Transtim which, when pressed, gives continuous transfer between whatever source and destination are selected; another key, labelled TCI gives, when pressed, continuous entry to TS COUNT for the words on IHW. Pressing a key called External Tree overrides the NIS, S and D parts of the word in TS COUNT and replaces them with the con- figuration set up on a row of 13 keys (one for each digit) also mounted on the Control Panel. There are keys for specifying the result of a discrimination indep- endently of the number transferred, for starting and stopping the Punch or Reader and for many other purposes. When considering the detailed operation of the Machine, we shall frequently come across signal lines to and from the Control Panel which have no part in the normal operation and are used only for usurping the normal arrangements in time of emergency. NS-y-37/11-57

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LOGICAL DIAGRAMS

Having put the DEUCE together as rapidly as possible, we may now take it apart at our leisure and examine the component sections. Before doing so we must expand one of two of the many over-simplifications in the preceding paragraphs and introduce the notation which will be used to describe the operation in detail. WIDE AND NARROW PULSES Within the Computer, the pulse interval is always 1 microsec, but the width of the pulse representing a digit "1" may take either of two values, depending on the point in the Machine at which the pulse train appears. (a) Narrow Pulses Pulse width about 0.3 microsec. There is a clear gap between two pulses representing adjacent "1"s. This type of signal may be fed through an a. c. coupling, and is mainly used in connec- tions between units. (b) Wide Pulses Pulse width 1 microsec. A row of "1"s and a row of "0"s are represented respectively by two different d.c. levels. This type of pulse is normally used in arithmetic units, where successive digits of two input signals are combined to generate the pulses of a waveform representing, say, the sum of the numbers coming in. This technique eliminates most of the effect of the timing errors inevitable at these speeds of operation. For instance, a timing difference of 0.2 microsec between the two input waveforms would remove two-thirds of the overlap bet- ween two narrow pulses, while the period of coincidence between two wide pulses would be cut by only 20%. Wide pulses are also used in the DELAY elements of the storage, in this case modu- lating a carrier signal of frequency 16 Mc/s. The three possible signals representing the number "13" are shown in Figure 3.1. In the first two cases, either positive or negative pulses may be used. Since the types of signal are used for different purposes, it is often necessary to generate signal (b) from signal (a) and vice versa. LOGICAL DIAGRAMS AND SYMBOLS In describing the operation of parts of the DEUCE, three main types NS-y-37/11-57

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of diagrams will be used. Two of these, the circuit diagram and the conventional "block schematic", need no explanation. The third type, which is peculiar to this kind of work, is the Logical Diagram. This also consists of a number of symbols connected together by lines which carry signals. The nature of these signals, however, is not specified; they are either present or absent, and have no other characteristic. Each symbol represents a logical unit which gives an output signal completely determined by its one or more input signals. The electronic circuit by which this required effect is achieved may take any of a number of forms, but the same logical symbol is used for all. Each line is marked with an arrow, and can convey a signal in only one direction. The polarity of a signal has no place in a logical diagram, nor have such units as power amplifiers. It is even possible to give a complete logical diagram of the DEUCE without referring to wide and narrow pulses. This will not be attempted here, since the present object is to explain the operation of the Machine in terms of its circuits, using logical diagrams only as an immediate stage. A logical diagram may be regarded as dealing directly with numbers, a signal which is present in alternate microsecs, for instance, being written "010101 ...". LOGICAL SYMBOLS The logical symbols which will be used in this report are set out in Figure 3.2 and described below. Typical input anal output signals are given in each case: One-Gate A signal appears at the output whenever a signal is applied to either (or both) of the two inputs. In cases where simultaneous signals at the two inputs cannot occur, the One-Gate may be replaced by a simple connection. Inhibitor-Gate The signal at the normal input (A) appears unchanged at the output, provided there is no signal at the inhibitor input (B). With a signal at the inhibitor input, there is no output, whatever the normal input. Two-Gate A signal appears at the output only when one is applied to both of the two inputs. In practice, at least one of the two inputs to any gate must have wide pulses, to avoid timing difficulties. General Gate This has any number of normal and inhibiting inputs and is marked NS-y-37/11-57

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with the number "n". Output signal occurs Only if "n" or more of the normal inputs carry signal, and none of the inhibiting inputs do. Negator A negator has one input and one output Connection. It gives a signal at the output if, add only if, no signal is applied to the input. Unit Delay The input is exactly reproduced at the output, except that each digit appears 1 microsec later. Longer or shorter delays are indicated by writing the delay, in microsecs, inside or beside the "D". Beginning Element This gives a single pulse at the output starting coincidentally with the beginning of any continuous signal at the input. End Element This gives a single pulse at the output starting coincidentally with the end of any continuous signal at the input. For a particular begin- ning or end element, the duration of the "single pulse" at the output is fixed by the values of the electronic components. There are a large number of such elements in the Computer, with output pulses varying from a small fraction of a microsec to several millisec, depending on the function which the output signal is required to perform. The exact width of the output pulse is never critical; its approximate duration will in general be clear from the context. Trigger A signal at the trigger input (J) is said to "stimulate" the trigger or to put it on. One at the inhibitor input (K) "clears" the trigger, or puts it off. So long as the trigger is on it gives a continuous signal at the output which represents a succession of "1"s. A signal at the trigger input while it is on, or one at the inhibitor when it is off, has no further effect. The output is always in the form of wide pulses. The inputs may be either wide or narrow pulses, or, in fact, any other form of signal pattern. Changeover Trigger This trigger is stimulated and cleared by alternate signals at the same input. A signal arriving while the trigger is off puts it on, and vice versa. NS-y-37/11-57

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Widener A narrow pulse of signal at the input initiates a 1 microsec pulse of signal at the output, beginning the same time as the input signal. It will be seen from the figure that the centre of the widened pulse is nearly half a microsec later than the centre of the original narrow pulse; thus a widener always introduces a concomitant delay of about half a microsec. Longer Delays Delays of 32 microsec or more used in the high-speed store will be denoted by a box with the delay period written inside. Composite Gate This has two outputs, one giving signal only when the two inputs differ, and the other giving a signal only when there is signal at both inputs. The diagram shows how these functions could be built up, as they usually are, by combination of previous symbols. The special symbol has been introduced here to give closer correspondence with the electronic circuit. Input Signals The operation of the computer may be modified by an external stimu- lous from the Main Control Panel or elsewhere. A source of such stimuli is represented by a square box with one output connection which carries signal when the source is stimulated and not otherwise. Examples of Logical Diagrams Figure 3.3 shows two small examples of the use of these symbols in combination. Multiway Gate To connect a selected one of five input signals on to a common out- put line, a control signal is sent to the appropriate 2-Gate and to none of the others. So long as this signal is maintained, this Gate gives an output which is the same as its input; the others give no output at all. A similar circuit will connect a common input signal to a selected one of several output lines. Changeover Gate A single control signal is used to choose between only two alterna- tive connections. With no control signal, input 1 passes through Gate A to the output and gate B gives no signal. When a continuous central NS-y-37/11-57

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signal in applied, Gate A is inhibited and gate B gives a signal which reproduces input 2. Source and Destination Gates Figure 3.4 shows a few bits of the Machine drawn in the new notation. The "Highway Amplifier" box at the top is a power Amplifier which intro- duces a short delay (about 0.15 microsec); for this reason, the sections of Highway connected respectively to the Sources and to the Destinations are called "Highway (Early)" and "Highway (Late)" Pulses on Highway are always narrow; each delay line therefore has on associated widener, modulator, detector and clock-pulse gate; these are not shown in the diagram. Signal is always supplied to just one of the lines S0, S1 ... S31, and one of the lines DO, D1 ... D31 and one of the lines N0, N1 ... N7. The Destination selector signal is effective only in conjunction with Transtim. NS-y-37/11-57

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FUNDAMENTAL WAVEFORMS

The operation of the DEUCE is controlled by certain basic waveforms Which determine the timing of the digits and, where necessary, distinguish Between the digits of a word. CLOCK PULSES This signal is a continuous sequence of pulses, 0.3 microsec wide, at 1 microsec intervals. It is used in converting a word from wide to narrow pulses, and thus controls the timing of digits throughout the Machine. A "Clock-Pulse Gate" is shown in Figure 4.1. Q-PULSES There are 32 of these signals, corresponding with the successive digits of a word. They are known as "Q1", "Q2", and so on, up to "Q32". Each consists of a 1 microsec pulse repeated every 32 microsec; it would represent, in wide pulses, a number with 31 zero digits and a "1". In Q1, this single pulse coincides with the first digit of a word; in Q2, with the second, and so on. The signals are shown in Figure 4.2; they are used to initiate any action required at a particular time in the minor cycle and to pick out a particular digit from a word. This second function is important in interpreting instructions and in the input and output mechanisms. The narrow equivalent of a Q-pulse is a "P-pulse". Only a few of these are used, and they are generated from the corresponding Q-pulse by a Clock-Pulse gate in the particular chassis where they are wanted. THE INPUT DYNAMICISER The number is first presented to the Machine in parallel form, that is with all the digits there at once, spread out across a row of relays or of holes punched in a card. Before it can reach the storage or the arithmetic units, the number must be translated into serial form, with all the digits appearing on a common line, one after another. This is done in a set of 32 circuits known collectively as the "Input Dynamiciser". The first six stages of the I.D. are shown in Figure 4.3. The switches which are "on" represent energised relays or holes punched in one row of a Hollerith card. The others are unenergised relays or blank spaces on the card. They are set in the diagram to represent the number 13. In successive microsecs Q1 flows through its switch to the common NS-y-37/11-57

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line, Q2 appears, but gets nowhere, Q3 and Q4 go through and Q5 and Q6 are baulked. The final signal is shown before and after "clocking". THE OUTPUT STATICISER The reverse translation from serial to parallel form is needed before a number can be displayed on a row of lamps or punched on a row of a card. This is done by the Output Staticiser, six stages of which are shown in Figure 4.4. The input signal is again the number 13, expressed in narrow pulses. Suppose that initially, all the triggers are off. In the first microsec, a narrow pulse arrives at the input and is presented at all the 2-Gates; at this time, only the Q1 line carried a signal, so only this gate gives an output, which stimulates the first trigger. In the second microsec, no pulse appears at the input, and nothing happens. Two succes- sive pulses now arrive, the first combining with Q3 to give an output which stimulates the 3rd trigger, and the second coinciding with Q4 to put the fourth trigger on. No further pulses arrive at the input, and none of the remaining triggers in struck. The number 13 is now represented in parallel form by signals coming from only the 1st 3rd and 4th of the row of 32 triggers. These triggers are connected either to the 0.S. lamp on the Control Panel or to the magnets in the Hollerith Punch which control the punching. Before a second word can be set up on the O.S., all the triggers must be cleared by a signal on the "Clear O.S." line. When using the row of lamps, this signal may be supplied either by obeying the Instruc- tion "18-24" which uses Destination Triggers, or by pressing a key on the Control Panel. When punching numbers on a card, the signal is auto- matically supplied by the Hollerith Punch as soon as each row has been punched. To staticise or dynamicise a word takes a time of 32 microsec. This causes no difficulty, since a row of a card remains under the read brushes or punch knives for much longer than this. So far, we have considered input and output only in binary form; no extra provision is made for decimal input and output, since a card is read or punched one row at a time as a sequence of twelve binary configurations, even if the pattern of holes in it is intended to represent one decimal number. The problem of combining these twelve configurations to form the same number in binary form, or of creating them from a single binary number, is one of programming rather than Machine design. THE OSCILLATOR The fundamental timing waveform is generated by an oscillator circuit, controlled by a crystal to a frequency of exactly 1 Mc/s. This signal ultimately controls the timing of individual digits throughout the DEUCE. Three connections are taken from the oscillator, as shown in Figure 4.5. NS-y-37/11-57

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From the lowest of the three output connections shown, the original 1 Mc/s signal is taken to the Divider where it controls, eventually, the timing of the Q-Pulses. The Clock-pulses are generated directly from the 1 Mc/s signal in a Shaper circuit, and transmitted through a power amplifier to the middle Output connection. The amplifier is needed because of the large number of points in the Machine to which this terminal is connected, and the correspondingly large output capacity. Between the oscillator and the divider is a phase-shifter circuit incorporating a manual control; varying this adjusts the timing of the Q-Pulse signals relative to the Clock-pulses (Figure 4.6). The signal at the upper output connection is an 8 Mc/s sine wave; this is connected to every storage position, in each of which the frequency is again doubled to give the 16 Mc/s signal which provides the carrier wave in the mercury delay lines. THE DIVIDER The main object of the Divider is to generate from the original 1 Mc/s waveform an output waveform with a period of 32 microsec. This is subsequently used to drive, in succession, the 32 circuits generating the Q-Pulse waveforms. There are also two outputs which control the precise timing of the Q-pulses. The logical arrangement of the divider is shown in Figure 4.7. It Consists mainly of a chain of five changeover triggers connected together with beginning elements. The first is operated by the 1 Mc/s waveform; it is therefore on and off for alternate periods of 1 microsec, giving a waveform at B whose total period is 2 microsec. A narrow pulse is therefore applied to the second trigger every 2 microsec; this trigger is thus on and off for alternate periods of 2 microsec, giving a narrow pulse every 4 microsec at F. This process continues until, finally, a narrow pulse occurs at L once every 32 microsec, coincident with one of the pulses at D which drive the Divider from the second stage onward. The pulses at K1 and K2, each with a period of 2 microsec, are Exactly interleaved. The K1 signal controls the end of every odd Q-pulse, that at K2 the end of every even Q-Pulse. Trigger "DRS" is stimulated every 32 microsec by the pulse at L, and cleared by the next K1 pulse, 1 microsec later. Its output signal, however, lasts for slightly less than 1 microsec, since the pulse at L is in practice later than the corresponding K2 Pulse, owing to the circuit delay in the last four divider stages. The final output at N, or "R(out)" is thus a pulse occurring every 32 microsec, truly coincident in time with one of the K1 pulses. This pulse is used to initiate the Q32 pulse. The vertical lines at the bottom of the waveform chart indicate the end of successive minor cycles. NS-y-37/11-57

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RING STAGES The Q-pulses are generated by 32 identical circuits, called "Ring Stages". Figure 4.8 shows the connections between the R(out) signal from the Divider and the first five ring stages. Each ring stage comprises a trigger and an End element. The trigger is stimulated by the clearing of the previous trigger, and cleared alternatively by a pulse from K2 and K1. The operation is clear from the waveform chart. The other 27 ring stages follow in just the same way; the last trigger is cleared just as the next pulse arrives at R(out) from the Divider to restimu- late the first. No use is made of the narrow output pulse from the last End element, which is left unconnected. The narrow pulses marking the microsecs are separated on to the two lines K1 and K2 because if they were all presented on one common line, the stimulating and clearing pulses to each trigger would arrive simultaneously. NS-y-37/11-57

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THE CIRCULATION UNIT

The first part of the machine to be described in detail will be the Circulation Unit, one of which is associated with each delay line storage position. There are 22 of them, all identical; special facilities such as the addition and subtraction into TS13 are attached by connecting an appropriate special unit to certain connection points which are provided on all circulation units but not always used. The layout of a storage position is shown in block form by Figure 5.1. It will be explained by tracing the passage of a signal round the loop, starting at the point "H". The Signal at H, consisting of narrow pulses, enters the Widener, a standard circuit from which the digits emerge as wide pulses. These go to the Modulator, where they modulate a 16 Mc/s carrier wave, generated by the Frequency Doubler from the common 8 Mc/s signal which enters the circulation chassis from a screened cable. The signal leaves the Circulation Unit in this form through a screened cable which takes it to the Transmitter; this is contained in a small box mounted near to the mercury column. In effect, it generates a powerful copy of its input signal, which it sends along a further screened cable to a Piezo-Electric Crystal which is in intimate contact with the mercury. The function of this crystal is to vibrate in sympathy with the applied electrical signal, and so to transmit sound waves of the same frequency, which travel through the Mercury Delay Line. At the far end of the delay, the pulses of sound hit a second Piezo- Electric Crystal, which has the reverse function of accepting the acoustic waves and giving out electrical signals of the same frequency. These pass through a Transformer which matches the impedances of crystal and cable (there is one at the input end. too), and through a screened cable to the Receiver. This is mounted near to the delay, and it revives the pulses, by this stage rather weak, before sending them through another screened cable back to the Circulation Unit. The signal new passes through the Detector, which removes the 16 Mc/s element and emerges as wide d.c. pulses. A conventional Clock-Pulse Gate is used to generate two narrow-pulse signals; that at "J" represents the words being stored, while the digits at "N" are the negated version. In most cases, J is connected to K, and N is not used. In certain Storage positions, however, the signal is taken from J (and also from N, in some form of them) to a special unit of some kind; such a unit must have, among others, one output terminal where the signal J emerges unchanged in form, so that it can be connected back to K and so complete NS-y-37/11-57

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the circulation path. An example is the Logical Operations unit, which takes signal from both J14 and N14 and returns a signal to K14. (The Logical Operations unit also takes signal from J15 and N15, but without breaking the circulation path of TS15). From K the narrow pulses pass to the Source Gate, which is connected to Highway (Early), to one of the outputs of the Source Selector Tree and to a point called SC which will be explained later. Before entering the Destination Gate, to which is connected the TT signal, an output from the Destination Selector Tree, and HWL, the signal passes through a Delay Network, which introduces a delay of 0.15 microsec. The precise object of this delay, which compensates for the delay in the Highway amplifier, will be discussed below. The Source and Destination connections are a little more complicated than so far explained (see section on "Selector Trees"). Next comes the NIS gate; in the first eight Delay lines, this is connected to the NISC line, IHW and the NIS Tree. The signal emerges at G Normally, G is connected directly to H; in some cases, however, the signal at G passes through a special unit. From which it emerges in the same form to be returned to H. An example is TS13, in which is inserted the Adder Unit. This completes the circulation path; the words in store circulate indefinitely, until replaced by a new input at the Destination gate. They may, however, be modified by the special units inserted at J-K or G-H. REGENERATION The passage through the mercury and the processes of modulation and Detection introduce a degree of distortion in the signal. Also, although the length of each mercury column is adjustable, there is bound to be some error of timing. However, so long as the pulse reaching the Clock- Pulse gate is large enough to be recognisable, and so long as it is not so wide, narrow, late or early that one or both of its edges reaches the Clock Pulse on either flank, the output from the Clock-Pulse gate is just as sound in shape and timing as that which would be generated by a perfect input pulse. The errors of shape and timing are thus not cumulative; if a pulse will make one lap of the circuit without harm, then (with reasonable margins of safety) it will circulate unharmed indefinitely, TIMING The Widener, as has been pointed out, effectively introduces a delay of about 0.35 microsec; this, as well as the delay network between K and G, must be compensated by shortening the mercury line to give a delay about 0.6 microsec less than its official value. NS-y-37/11-57

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In some cases, a special unit inserted at J-K or G-H introduces a delay of 1 microsec; these delays must also be compensated by a corres- ponding shortening of the mercury line. A pulse at K occurs at the same time as the corresponding digit on HWE but about 0.15 microsec before that HWL. The effect of the delay network is that a pulse has the same timing at H whether it came straight through from K or had just entered at the Destination gate. In consequence, all pulses arrive at the Clock-Pulse gate with the same timing, giving a greater margin of error than would be obtained if a range of different input timing had to be safely accommodated. INDIVIDUALITIES The 22 Circulation Chassis are identical, and each contains the same equipment, including the Source, Destination and NIS gates. Not all of these, however, are connected in the standard manner described above. In the 21 storage positions, the Source and Destination gates are all normal, as are the NIS gates of the first eight Delay Lines. The other NIS gates are not used, the NISC, IHW and NIS Tree terminals being left unconnected. In TS COUNT, none of the three gates is normally connected. They are all used for special purposes which will be described in the chapter on Control. NS-y-37/11-57

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CONTROL

THE INSTRUCTION WORD The Instruction word comprises seven separate numbers of up to five digits each. Digits Name, Possible Values and Function 2 to 4 NIS (0 to 7) Number of Selected NIS gate. 5 to 9 S (0 to 31) Number of selected Source gate. 10 to 14 D (0 to 31) Number of selected Destination gate. 15 & 16 C (0 to 3) Characteristic. Determines the length of Transfer as explained below. 17 to 21 W (0 to 31) Wait number. Number of idle minor cycles between Set-up and 1st m.c. of Transtim. 26 to 30 T (0 to 31) Timing number. Specifies the m.c. of the next instruction and sometimes the last m.c. of Transtim. 32 G (0 or 1) Go digit. Function explained in conjunc- tion with details of Control. Digits 1, 22 to 25 and 31 are spare; they are ignored by Control and their value has no effect on the operation. CHARACTERISTIC NUMBER The function of the Timing number is modified by the value of the Characteristic, which effectively divides Instructions into three types, each of which is given a special name: Single Transfer - C is 0. Transfer is for 1 m.c. only. Long Transfer - C is 1. The number of m.c. for which TT is applied is determined by the values of W and T. NS-y-37/11-57

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Double Transfer - C is 2. Transfer is for just two minor cycles. (The Characteristic is not normally given the value 3). The details of timing will first be described for a Long Transfer. TIMING OF TT AND TCI SIGNALS FOR A LONG TRANSFER Figure 6.1 gives an example of the timing of TT and TCI in a Long Transfer (C = 1) in which W is taken as 2 and T as 4. The Instruction in question is stored in m.c. 7 of some DL; it appears on IHW in this m.c., and is let into TS COUNT by the application of TCI Signal. In m.c. 8 the Instruction first enters the main part of Control from the delay element of TS COUNT, and the various gates are selected in accordance with the NIS, S and D numbers. Minor cycle 8 is thus the Set-up m.c. After Set-up, there is a pause of W m.c.; in the figure, W is 2, and the pause occupies minor cycles 9 and 10. If the Wait number were 0, Transtim would first have been applied in m.c. 9; as it is. Transfer commences in m.c.11. The Timing number has a dual function, affecting both TT and TCI. The last minor cycle of Transfer, which is also the single m.c. for which TCI is applied, is the T + 1th after Set-up and the T + 2th after that in which the Instruction was stored. In the example, this is the 5th m.c. after Set-up, or m.c.13. The transfer occupies minor cycles 11, 12 and 13. The next Instruction enters TS COUNT in m.c.13. It must therefore have been stored in m.c.13 of the Delay Line referred to in the NIS number. It enters TS COUNT while the Transfer specified by the previous Instruction is still in progress, but it does not affect the operation until the following minor cycle, in which it first enters the main part of Control. Its NIS, S and D numbers are set up in m. c.14. GENERAL CASE The minor cycles of operation are usually referred to the minor cycle in which the current Instruction is stored, and in which (by definition) it enters TS COUNT. We will call this minor cycle "m". The Set-up minor cycle is m.c. m + 1. Transfer commences in m.c. m+w+2. The next Instruction is stored in m.c. m+T+2. (These three numbers hold for any value of Characteristic). The last m.c. of Transfer Is m+T+2, so that the number of minor cycles of Transfer is T-W+1. NS-y-37/11-57

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W GREATER THAN T The last minor cycle of Transfer clearly cannot precede the first. If W exceeds T, the effective value of T is increased by 32. Minor cycle m+T+2 is ignored, Transfer starts In m.c. m+W+2; the minor cycle in which Transfer ends and the next Instruction enters TS COUNT is m.c. m+T+34, or m+T+2 of the next Major Cycle. The next Instruction is still stored in m.c. m+T+2, but only at its second appearance on IHW is the TCI gate opened to let it into TS COUNT. As an example, take an Instruction stored in m.c.27 whose Wait and Timing numbers are 10 and 1 respectively. The minor cycles of Transfer are from 39 to 62, that is from 7 to 30 of the next Major Cycle. The next Instruction is stored in m.c.30, and enters TS COUNT at its second attempt. SINGLE AND DOUBLE TRANSFERS The minor cycles in which Transtim commences and in which TCI is applied are the same for all values of C, being m+W+2 and m+T+2 (or m+T+34) respectively. The Characteristic affects only the end of Transtim. If C is 0, Transtim is applied for only one minor cycle, m+W+2; if C is 2 Transtim is applied for two minor cycles, m+W+2 and m+W+3. The effect of Single and Double Transfer Instructions is shown in the diagram by dotted lines. When W = T and C = 2 the next Instruction cannot enter TS COUNT in m.c. m+T+2, since this would precede the second minor cycle of transfer m.c. m+W+3, specified by the Characteristic. Instead, in this special case, its next Instruction enters TS COUNT in m.c. m+T+34. DETAILED OPERATION OF CONTROL For simplicity, the logical diagram of Control will be given in sections, illustrating only that part currently under discussion. Figure 6.2 shows two features, the detailed input mechanism and the Unit Subtractor, represented as a block. DESTINATION 0 Normally, the word entering TS COUNT comes from IHW, which is con- nected only to the first eight Delay Lines. It is possible, however, by using Destination 0, to inject into TS COUNT any word which is available at a Source. If D0 is selected, and TT is applied in the same minor cycle as TCI, the word entering TS COUNT will be the one appearing in that minor cycle, not on IHW, but on HWL. Suppose, as an example, that the word currently in TS16 represents the Instruction which is to be obeyed next. A preliminary Instruction is necessary which might be: NS-y-37/11-57

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N S D C W T X 16 0 1 0 5 This preliminary Instruction reaches TS COUNT in. say m.c.9 in the usual way, through IHW, having been stored in m.c.9 of one of the first eight DLs. S16 and DO are set-up in m.c.10, and TT is applied from m.c.11 to m.c.16. During this time, the word in TS16 is repeatedly applied to the TCI input gate to TS COUNT. From m.c.11 to m.c.15, this gate is shut, but finally, in m.c.16, TCI is applied and the word from TS16 enters TS COUNT. The Wait and Timing sections of the word in TS COUNT must be calculated as if the word had been stored in m.c.16 of one of the first eight Delay Lines. The NIS number of the preliminary Instruction is immaterial, since it affects only the words on IHW, none of which succeeds in reaching TS COUNT. This procedure uses two Instructions, the preliminary one and the one in TS16, to obtain one useful Transfer, that specified by the Instruction in TS16. The facility is very useful, however, for the initial input of Instructions from the Hollerith Reader and for using Instructions which have been modified in some way by the arithmetic units. The TCI gate, by the way, is the normal Destination Gate in the TS COUNT circulation unit. THE UNIT SUBTRACTOR (FUNCTION) The Unit Subtractor takes in the Instruction word at "A" and sends it out again at "B", unchanged except that 1 has been subtracted from each of the Wait and Timing numbers. If the word at "A" is "N,S,D,C,W, T,G", it will emerge from "B" as "N,S,D,C,W-1,T-1,G". The values of T and W are thus decreased by 1 for each circulation through TS COUNT. The Unit Subtractor also gives signals at "C" and "D", which indicate when the Wait and Timing numbers, respectively, have been reduced to zero. "C", which gives a signal W m.c. after the Instruction entered TS COUNT, initiates the start of TT, and "D" initiates the end of TT (if the Characteristic is 1 in the Instruction) and the m.c. of TCI. Finally, the Unit Subtractor gives a signal at "E" which consists of the Instruction word negated. This goes to the circuits which select the appropriate NIS, S and D. UNIT SUBTRACTOR (OPERATION) Two examples will first be given of the subtraction of "1" from a binary number (least significant digit on the left). 1 2 4 8 16 1 2 4 8 16 0 0 1 1 1 (28) 0 1 0 0 0 (2) 1 1 0 1 1 (27) 1 0 0 0 0 (1) NS-y-37/11-57

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In each case, the lower number could have been obtained from the upper by negating all digits up to and including the first "1" and leaving the others unchanged. This procedure, in fact, always has the effect of subtracting "1" from the number to which it is applied, and forms the basis of the operation of the unit Subtractor. The details of the Unit Subtractor are shown in Figure 6.3. The connection marked "from Trigger S" is associated with the double transfer operation and may be ignored for the moment. The Instruction word emerges from the TS COUNT delay element in wide-pulse form; the points "J" and "N" both carry narrow-pulse words, at "J" the Instruction word and at "N" the same word negated. This clock-pulse gate is the normal one in the TS COUNT circulation unit. The signal emerging at "B" will be the "J" signal if Trigger CARRY is off and the "N" signal if it is on. The word "J" is thus returned unchanged to "K", except that those digits which occur while Trigger CARRY is on are negated. Trigger CARRY is stimulated by very narrow pulses of signal which mark the back edges of Q16 and Q25. It is cleared at the end of any microsec in which a digit "1" appears at "J". Figure 6.4 shows the outputs from CARRY and at "B" in response to an input word at "A" whose Wait and Timing numbers are 28 and 2 respectively; 1 has been subtracted from both W and T. The output from CARRY includes neither Q22 nor Q31, so there is no output from "C" or "D". "C" gives an output only if the signal from CARRY extends to cover Q22, which means that all the five Wait number digits at "A" must be zero. This occurs in m.c. m+W+1, where the original Instruction entered TS COUNT in m.c. "m" and had Wait number "W". The subtraction process continues, and the W section of the word at "A" is again zero after a further 32 unit subtractions, giving a second pulse of signal at "C". The output at "C" is thus P22 in m.c. m+W+1, and in m.c. m+W+1 of every subsequent Major Cycle until the word in TS COUNT is replaced by the next Instruction. Very often, the Instruction is replaced before the second signal is due at "C" which then gives only one pulse for each Instruction. Similarly, the output at "D" is P31 in m.c. m+T+1, of every Major Cycle until the Instruction is replaced. Figure 6.5 shows the operation for zero Wait and Timing numbers at "A", though these, in practice, occur in the same minor cycle only if the original W and T were equal. The Timing number at "J" now provides no signal to clear Trigger CARRY, which is therefore extinguished by the front edge of a Q32, to prevent its remaining on and negating Go digit and possibly part of the NIS number. Trouble would also arise from a pulse at P16 or P25 time at "J", which would try to clear Trigger CARRY just at the moment when other pulses were arriving to stimulate it. This is avoided by removing any such digits by an inhibitor gate. NS-y-37/11-57

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THE INSTRUCTION STATICISER The signal from "E" is used to select the required NIS, S and D gates. It is first taken to a set of 14 circuits called the "Instruction Staticiser". The output at "E" is therefore usually called the "IS" signal. The Instruction Staticiser, shown In Figure 6.6, may be des- cribed as a negated version of part of the Output Staticiser. Its output is a parallel version of 14 digits of the word in TS COUNT. In the Output Staticiser, the "Clear OS" signal puts all the OS triggers off, and individual ones are put on by pulses at the appropriate time in the OS input word. In the Instruction Staticiser, on the other hand, the "Clear IS" signal puts all the IS triggers on, and individual ones are put off by pulses at the appropriate time in the IS input word from "E". The "Clear IS" signal is a short pulse at the end of the TCI signal; it therefore occurs just as a new Instruction has finished entering TS COUNT but before it emerges in negated form at "E". Suppose, for example, that this new Instruction has NIS number "6", meaning that its 2nd, 3rd and 4th digits are 0, 1, 1 respectively; the corresponding digits at "E" are 1, 0, 0. The IS signal has a pulse in Q2 time, which clears Trigger IS2, but not during Q3 or Q4; triggers IS3 and IS4 thus remain on. The next 11 digits, up to the 15th, are staticised in the same way; this process takes place during the set-up minor cycle, at the end of which, the IS trigger outputs give the static equivalent of the "Address" section (digits 2 to 15) of the word in TS COUNT. The (negated) word in TS COUNT appears repeatedly on IS, but the IS triggers are unaffected after the first time; the subtracting process does not affect the Address section so that the pulses are merely applied to the "Clear" input of triggers which are already off. The pulses are inhibited while TCI signal is applied to let the next Instruction into TS COUNT; the reason for this will become clear when we consider the discrimination facilities. THE EXTERNAL TREE The outputs of the first 14 IS triggers (IS2 to IS15) may be replaced with signals from 13 "IS Keys" and a "Characteristic Key" on the Control Panel. This is done by pressing another key on the Control Panel called "External Tree". SELECTOR TREES (FUNCTION) 13 of the IS trigger outputs are taken in groups to three "Selector Trees" represented in Figure 6.7 by blocks. The IS2, IS3 and IS4 signals, for instance, go to the NIS Selection Tree; this then gives an output on one of eight possible output lines. Which of the output lines is chosen NS-y-37/11-57

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at any given time is determined by the particular one of the eight pos- sible binary configurations then being applied at the three IS input lines. The Source and Destination Selector Trees are also shown as blocks, each having five IS input lines and 32 possible output lines. Their operation is more complicated than that of the NIS Tree, and some further explanation will be given at the end of the description of Control. The output of trigger IS15, representing the first digit of the Characteristic number, is taken, not to a Selection Tree, but to the Section of Control governing the operation of Transtim. TRIGGER R AND Q The N, S and D numbers of the Instruction word determine the IS trigger settings, which in turn control the three Selector Trees. The Wait and Timing numbers determine the minor cycles in which signals occur at "C" and "D"; these signals, in turn. control the operation of TT and TCI. In the first place, the signals at "C" and "D" operate two triggers, Trigger R and Trigger Q, as shown in Figure 6.8. Trigger GO, also shown in the diagram, will be assumed to be permanently on; its operation will be ignored for the moment. The output of the two triggers is shown in Figure 6.9 which also gives, for comparison, the required TT and TCI signals. Trigger GO being on, Trigger R is stimulated by the first pulse of signal at "C", which occurs at P22 of m.c. m+W+1; Trigger Q is stimu- lated by the first pulse of signal from "D" after Trigger R has been put on. If T is less than W, the first signal at "D" has no effect, and Trigger Q comes on at P31 in m.c. m+T+33; otherwise, at P31 in m.c. m+T+1. If T and W are equal, the two triggers are stimulated at P22 and P31 in the same minor cycle (except, as we shall see, in the case of a double transfer). Trigger Q stays on for less than one minor cycle, being stimulated at P31 and cleared at the beginning of the next Q22 signal. Trigger R is also cleared at this time, by a short pulse occuring at the end of the signal from Trigger Q. The output of Trigger R governs the generation of the Transtim signal; it is also used in the Discrimination facilities, which have yet to be described. The output of Trigger Q governs the generation of TCI. TRIGGERS S, P AND TT Figure 6.10 shows the part of Control which generates the Transtim signal. The signals from the various triggers are given in Figure 6.11. There are three possible modes of operation. depending on whether the Transfer is to be Long, Single or Double. NS-y-37/11-57

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In all three cases, Trigger P comes on at the same time as Trigger R. In a Long Transfer there is a signal from Trigger IS15, and Trigger P remains on until it is cleared by a short pulse at the end of the signal from Trigger R. The outputs of Triggers R and P are thus identical. Trigger TT is controlled by short pulses of signal at P32 time; its output is passed through a delay network of 0.5 microsec, so that the final output exactly spans one or more minor cycles. The point of this arrangement is that the 0.5 microsec delay can be shortened to compensate for any stray delays in the subsequent circuits. TT is stimulated by the first of these P32 signals after Trigger P comes on and cleared by the first one after Trigger P goes off. In the case of a Long Transfer, Trigger TT comes on at the end of m.c. m+W+1 and goes off at the end of m.c. m+T+2. In both Single and Double Transfer Instructions, the Characteristic is even, the 15th digit is "0" and IS15 is cleared by the IS signal and remains off throughout the operation. As we shall see, this means that a Q14 signal is released from gate "F" to clear Trigger P in either the first or second minor cycle after it is stimulated. The distinction between Single and Double Transfer Instructions is determined by Trigger S. This has the function of staticising the 16th digit of the Instruct on, but it differs in two respects from a normal IS trigger. Firstly, it is cleared by CIS and stimulated by a P16 pulse from "J" instead of being stimulated by CIS and cleared by a P16 pulse from "N"; secondly, instead of remaining on until the next Instruction enters TS COUNT, it is cleared in the coarse of interpreting and obeying the current Instruction. A point to note is that any P16 digit at "J" is inhibited in the Unit Subtractor at its first appearance, and makes no further attempt to stimulate Trigger S; once this is cleared, it there- fore is not restimulated until the arrival in TS COUNT of another Double Transfer Instruction. The detailed operation of the three types of Instruction will now be described. LONG: m.c. m+W+1 :- P comes on with R at P22; TT comes on at P32. m.c. m+T+1 :- Q comes on at P31. m.c. m+T+2 :- P goes off with Q and R at Q22; TT goes off at P32. SINGLE: m.c. m+W+1 :- P comes on with R at P22; TT comes on at P32. m.c. m+W+2 :- P goes off at Q14; TT goes off at P32. NS-y-37/11-57

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DOUBLE: m.c. m+W+1 :- as before. m.c. m+W+2 :- Q14 from gate "F" is inhibited by Trigger S; S goes off at Q19. m.c. m+W+3 :- P goes off at Q14; TT goes off at P32. It will be seen that Trigger S is always cleared before the CIS signal arrives at the end of m. c. m+T+2, the minor cycle of TCI. The CIS connec- tion is, in fact, necessitated only by the operation of the Discrimination facilities. A connection is taken from Trigger S to inhibit the signal from D which stimulates Trigger Q. If Trigger S is on, this prevents Triggers R and Q coming on in the same minor cycle, as required for a double transfer with equal Wait and Timing numbers. CONTINUOUS TRANSTIM Pressing a key on the Control Panel labelled "Cont T.T." injects a signal connected to the output of Trigger P. This causes TRANSTIM to come on at the next P32 and to stay on. The result is continuous transfer between the selected Source and Destination. PbD6 It is required for various purposes around the Machine to have a short signal which occurs a little before the beginning of Transtim. This is provided by taking a connection from Trigger P through a beginning element and a delay of 6 microsec (see Figure 6.10). The result is a brief pulse of signal at about P28 time in the minor cycle immediately preceding the first minor cycle of Transtim; this is known as "Trigger P (beginning) delayed 6 microsec", or PbD6 for short. It is used in Destination Triggers and a device called "Control-Magnetic Interlock" (CMI) which will be des- cribed in the next paragraph. CONTROL-MAGNETICS INTERLOCK In the chapter on the Magnetic Store, it will be found that any operation involving the Magnetics occupies at least 13 millisec. To save time, it is arranged that each such operation is initiated by an Instruc- tion obeyed in Control and then proceeds to completion under its own steam, leaving the rest of the DEUCE free to do any other sequence of operations required by the computation in hand. However, this method has the snag that while this first Magnetic operation is still in progress the program may proceed as far as a second Instruction intended to initiate a Magnetic operation, with the result that the Magnetics would be required to do two things at once, which it cannot. To avoid this trouble, the second Instruction is held NS-y-37/11-57

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suspended in TS COUNT until the completion of the first Magnetic operation, and the Program proceeds no further until this time. Let us state the requirements ware precisely: whenever (a) a Magnetic operation is in progress and (b) the Instruction about to be obeyed would initiate a further Magnetic operation then this Instruction is not obeyed but is held over until the completion of (a). The information (b) that a Magnetic operation is about to be called is taken into the Magnetics organisation by connections from the IS Triggers; here, it is combined with the information (a) that a Magnetic operation is already in progress to generate a warning signal which is taken to Control on a line called "Control-Magnetics Interlock" or CMI. The circumstances and circuits in which CMI signal is generated will be described in the chapter on Magnetics; these circumstances will be seen to be a little more complicated than has yet been indicated. Here we are concerned only in the action of CMI signal in suspending the operation of Control. The connections are shown in Figure 6.12. It will be remembered that PbD6 signal occurs at about Q28 time in m.c. m+W+1; if CMI signal is present, this PbD6 signal (gated with Q28 to fix the timing precisely) is used to clear Trigger R. Trigger P is in turn cleared by the end element connecting it with Trigger R; furthermore, Trigger Q never comes on, since Trigger R goes off at Q28 time and the earliest time at which Trigger Q could be simulated is at P31 in that minor cycle. The system then behaves as though Trigger R had never been stimulated, and waits for the next signal from point C, a Major Cycle later, to stimulate Trigger R again. Unless CMI has ceased by then, the second attempt will also be abortive. Only when the current Magnetic operation has finished and CMI come to an end, will a pulse from point C be allowed to bring Control into normal operation in obeying the Instruction which has up to then been circulating vainly in TS COUNT. It may not be clear why PbD6 Is needed at all; the operation des- cribed above could have been equally well achieved by taking CMI signal directly to clear Trigger R. However, with this arrangement an Instruc- tion initiating a Magnetic operation would always need equal Wait and Timing numbers, an irksome restriction for the programmer. The point is that as soon as Transtim comes on for such an Instruction, the Magnetic operation starts; since the Instruction at that time on the IS Triggers is one specifying a Magnetic operation, CMI signal starts immediately. If this were allowed to clear Trigger R by itself, Trigger Q would never NS-y-37/11-57

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come on to initiate TCI signal and call in the next Instruction; the only way round this would be for Trigger Q to have already come on before the start of Transtim, and this requires equal Wait and Timing numbers. The introduction of PbD6 gets over this difficulty, since the PbD6 signal always occurs before the start of Transtim and thus before the start of the CMI signal due to the Instruction which itself initiated the current Magnetic operation. The connection marked "Request Stop" in Figure 6.12 will be explained later. TRIGGER TCI Figure 6.13 shows the connections from Trigger Q to Trigger TCI, and the output signals of the two triggers. Trigger D, also shown in the diagram, is associated with the Discrimination facilities; for the present, it will be assumed to be always off. With this assumption, the relation between Triggers TCI and Q is exactly the same as that between Triggers TT and P except that the operating signal comes at the back edge of Q32, not at P32. Trigger TCI comes on at the end of the minor cycle in which Q is stimulated, and goes off at the end of the minor cycle in which Trigger Q is cleared. These two minor cycles, m+T+1 and m+T+2 are adjacent, so that TCI stays on for only one minor cycle, m+T+2 as required. CONTINUOUS TCI A key on the Control Panel labelled "Cont TCI" injects (when depressed) a continuous signal at the output of Trigger Q. This causes TCI to commence at the next Q32 (back) and to continue. TRIGGER GO (FUNCTION) From Figure 6.8 it is clear that if Trigger GO is off the signal from "C" will fail to stimulate Trigger R, and that this in turn will prevent the "D" signal from stimulating Trigger Q. Transtim signal is not applied to carry out the wanted Transfer, nor does TCI signal arrive to let the next Instruction into TS COUNT. The present Instruction remains in possession, and pulses emerge every Major Cycle from "C" and "D", ready to do their jobs as soon as a signal arrives from Trigger GO. When Trigger GO is finally stimulated, the Instruction is obeyed; all the minor cycles of action are correct, but everything happens a fixed number of Major Cycles after it would otherwise have occurred. Since the only effect of Trigger GO is on the signal from "C" which occurs at some P22 time, the state of the trigger at any other time in a minor cycle is immaterial. It will be seen that Trigger GO is cleared in the course of obeying each Instruction, and has to be stimulated by some means for each succeeding Instruction before it can be obeyed. NS-y-37/11-57

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Trigger GO, with the associated Trigger STOP is used to influence the action of Control from outside by means of three of the keys on the Control Panel (and also by means of operations of the Punch and Reader, as will be seen). The P32 or "go" digit of the Instructions is also concerned. One of the Control Panel keys, the "Stop key". has three positions called "Normal", "Stop" and "Augmented Stop". In the Normal position a digit "1" in the P32 position of an Instruction entering TS COUNT is allowed to stimulate Trigger GO. In a sequence of such Instructions, Trigger GO will be stimulated once for each, and operation will be normal as already described until an Instruction is reached whose P32 digit is zero (called a "Stop Instruction" or "Stopper"). This Instruction stays in suspended operation until a stimulus, called a "Single-Shot", is supplied from outside to stimulate Trigger GO. With the Stop Key In the Stop position, the P32 digit of the Instruc- tion is no longer allowed to stimulate Trigger GO. As a result, all Instructions are treated as Stop Instructions, and a Single-Shot signal must be given for each. The Augmented Stop position of the Stop Key again inhibits the action of the GO digit; it also brings the STOP Trigger into play. This trigger is now stimulated by CIS signal at the start of obeying every Instruction; it is cleared by the Go digit of a Go Instruction, but left on if the Instruction is a "Stopper". While the Stop Trigger remains on, Single-Shots are ineffective, and can no longer stimulate Trigger GO; neither the current Instruction nor any of its successors can be obeyed until Trigger STOP has been cleared. This can be done only by pressing the second of the three Control Panel keys concerned, the "Release Key". The net result of the Augmented Stop position is that a sequence of Go Instructions may be obeyed, as in the Stop position, by supplying a Single-Shot for each. As soon as a Stopper is reached, the Machine seizes up and will do nothing. The Release Key must be pressed before a Single- Shot will be effective in causing the Stopper to be obeyed. The third Control Panel key supplies the Single-Shots; it can be moved either up or down from its normal centre position. Pressing the Single-Shot Key once gives one Single-Shot. Raising the key starts a succession of Single-Shots at the rate of about ten a second. If the Stop Key is in its Stop position, this gives operation at about one two- hundredth of normal speed. Single-Shots alternatively come from the Reader or Punch whenever a card is passing. In either case, one Single-Shot is emitted each time a row of the card comes level with the reading brushes or punching knives. There are thus twelve Single-Shots for each card which passes through the Reader or Punch. This facility is used, in effect, to slow the DEUCE to the speed of a Hollerith machine when reading or punching numbers. To NS-y-37/11-57

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punch twelve numbers in binary form on a card, for example, the twelve Instructions transferring these numbers to D29 are all made Stoppers. Each of them remains suspended in TS COUNT till a card row comes into position, when a Single-Shop signal causes it to be obeyed. punching the number transferred on to the card. The DEUCE then proceeds at full speed to the next Stopper and then waits for the next row of the card. CONNECTIONS TO TRIGGERS 'GO' AND 'STOP' The connections are shown in Figure 6.14. The P32 digit of the Instruction is taken from the normal NIS Gate of TS COUNT to stimulate Trigger GO and from the normal Source Gate to clear Trigger STOP. In all other circulation units, Source Cathode signal (and NIS Cathode signals where the NIS Cathode is used at all) is permanently applied so that only the selection of the appropriate Source (or NIS) number is needed to bring the gate into operation. In this case, however, these signals are applied only at Q32 time, and can operate only to release the P32 digit on to HWE or IHW respectively. The actual operation of the two gates is done by direct connections from the Stop Key to the points where the signals from the NIS and Source trees respectively are normally applied. With the key at Normal, the NIS Gate is always operated and lets every Go digit through to stimulate the GO Trigger; in the Augmented Stop position the Source Gate releases every P32 digit in an Instruction to clear Trigger STOP. When the key is at Stop, neither gate is operated. The connection from the Augmented Stop position to the Source Gate, by the way, has no operational justification; it could equally well be replaced with a permanently applied signal. The arrangement adopted, however, permits a simplification in the electronic realisation of the logical diagram. The point is that the same Q32 signal is used alter- natively to operate the NIS Gate (Normal position) to do nothing (Stop position) or to operate the Source Gate (Augmented Stop position). If this signal were used permanently in the Source Gate whatever the position of the Stop Key, a second Q32 signal would have to be supplied to operate the NIS Gate in the Normal position. (These remarks can be fully under- stood only by reference to the electronic circuits concerned). For any Instruction to be obeyed, Trigger GO must be stimulated, either by a Go digit or by a Single-Shot. At the end of obeying each Instruction, Trigger GO is cleared by a Q16 in the TCI minor cycle, the minor cycle in which the next Instruction enters TS COUNT. This is necessary in case the next Instruction is a Stopper or the Stop Key is in the Stop or Augmented Stop position. It also has the effect of prevent- ing Transtim during the Set-up minor cycle which immediately follows that of TCI. Figure 6.15 shows the relevant signals. Trigger Q is cleared at Q22 in the TCI m.c., clearing Triggers R and P (if it is still on) at the same time. Trigger R cannot immediately be stimulated by any signal at point C because Trigger GO is now off. Trigger R is therefore still off at the end of this minor cycle, and Trigger TT is then cleared; TT NS-y-37/11-57

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cannot be restimulated until the next P32 time, which occurs at the end of the Set-up minor cycle. The Go digit is taken to Trigger GO from the NIS Gate which comes after the Destination Gate, rather than from the Source Gate which comes before it because Trigger GO would otherwise be stimulated by the Go digit of the previous Instruction. Furthermore, this arrangement avoids wasting a Major Cycle in the operation of a Go instruction with zero Wait number. For such an Instruction, the first signal from point C occurs while the Instruction word is emerging from TS COUNT for the first time (the Set-up minor cycle). If Trigger GO were not stimulated until the end of this minor cycle, the first opportunity of stimulating Trigger R would be lost. As things stand, Transtim signal starts immediately at the end of the Set-up minor cycle. It would appear at first sight that it does not matter at which point in the minor cycle a Single-Shot arrives to stimulate Trigger GO. It would be unfortunate, however, if this signal arrived between P16 and P22 in the TCI minor cycle, for this might allow Trigger R to be stimulated at P22 in this minor cycle, which would cause Transtim signal to occur during the Set-up minor cycle, while the Source and Destination numbers were changing. All this would only happen, of course, if a Single-Shot were applied while the Machine was doing a sequence of Go instructions with the Stop Key at normal; while this contingency is unlikely, it could arise and must be provided for. The provision made is to arrange that a Single-shot, at whatever time it originates, can supply a pulse to stimu- late Trigger Go only at Q32 time. This is the object of the two triggers shown in the path from the point SS (the Input of Single-Shot signals from outside) to Trigger GO. The detailed operation of these will be described in the Circuit Manual, since the reason for having two triggers rather than only one is purely electronic. It has been said that the connection from the Augmented Stop position of the Stop Key to the TS COUNT Source Gate is irrelevant; the effective connection from Augmented Stop is the one which permits CIS signal to stimulate Trigger STOP just as each successive Instruction has entered TS COUNT. If this is a Go instruction, its P32 digit will come out of the Source Gate to clear Trigger STOP; the action from then on will be just as though the key were in the Stop position. If, however, the Instruction is a Stopper, the Single-Shot signal cannot get through to stimulate the GO Trigger until Trigger STOP has been cleared by pressing the Release Key. More accurately, the STOP is cleared when the Release Key is allowed to return to its normal position; otherwise, if a stream of Single-Shots were being applied, several Stop Instructions might be obeyed in the Interval between pressing the Release Key and releasing it. It will be noticed that Trigger STOP is not cleared by a Go digit until the end of the Set-up minor cycle, This cannot cause any waste of time because two successive Single-Shots are never closer together then NS-y-37/11-57

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about 15 millisec (the interval between successive rows of a card passing through the Reader). The complete result of an effective Single-Shot, carrying out one current Instruction and taking the next into TS COUNT, can never occupy more than three Major Cycles, The GO and STOP Triggers each operate a lamp on the Control Panel which shows whether they are on or off. DISCRIMINATION FACILITIES The input arrangements to Trigger D, which are shown in Figure 6.16 incorporate two special Destinations, D27 and D28. An Instruction using either of these Destinations may cause Trigger D to be stimulated during the course of the Transfer; this will have the effect of modifying the action of Trigger TCI, so that it is no longer exactly as has been described. Assuming, for the moment, that there is no input signal at either "DN" or "DF", the digits appearing on HWL will always he applied effectively to gate K. If D28 is used, any signal on HWL during the Transtim period will pass through gate K to stimulate Trigger D. In other words, a sequence of numbers transferred to D28 will have no effect if they are all zero, but will stimulate Trigger D if any of them contains a digit "1". The action of D27 is similar, but In this case, Transtim signal has to pass through gate L, and reaches gate K only at Q32 time of every minor cycle for which it is applied. A sequence of numbers sent to D27 will stimulate Trigger D if, and only If, the 32nd digit of one or more of the numbers is a "1". In the Signed convention, this means that D is stimu- lated if any of the numbers is negative, but not if they are all positive. DN and DF are connections from a control panel key. Raising this gives signal on DF and ensures that Trigger D will not be stimulated by any transfer to D27 or D28. Lowering the key gives signal on DN and ensures that any transfer to D27 or D28 will stimulate Trigger D. The key is used in program testing. EFFECT OF TRIGGER 'D' Figure 6.17 shows the output signals of Triggers R, Q, D and TCI at the end of an Instruction using D27 or D28. The full and dotted lines give respectively the cases where Trigger D has and has not been stimu- lated. In both cases, Trigger Q comes on at P31 in m.c. m+T+1, and goes off, together with Trigger R, at Q22 in m.c. m+T+2. Trigger D is cleared by the first Q19 signal after Trigger R is cleared, that is at Q19 in m.c. m+T+3. Trigger TCI is stimulated at the end of the first Q32 signal after Trigger Q comes on, that is at the end of m.c. m+T+1. At the end of each NS-y-37/11-57

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subsequent minor cycle, since Trigger Q is now off, a pulse signal is applied to gate M (Figure 6.16), with the intention of clearing Trigger TCI. If Trigger D is off, this succeeds at the first attempt, giving the normal operation already described; when Trigger D has been stimulated during the Transfer, however, it is not cleared till midway through m.c. m+T+3; it therefore inhibits the first of the signals at gate M and TCI is not cleared until the end of m.c. m+T+3. Trigger D has no effect on the operation of Trigger TT, or on the IS triggers. Thus the final effect of these facilities is that if a non-zero number is transferred to D28, or a negative one to D27, TCI is applied not only for its normal period of one minor cycle, but also for the minor cycle immediately following. EXTRA MINOR CYCLE OF TCI Each Instruction specifies its successor by means of its NIS and T numbers. Normally, this is determined uniquely, and the next Instruction is the word stored in m.c. m+T+2 of DL"N". This word, which we shall call "NIA", is let into TS COUNT by the application of TCI signal for the minor cycle m+T+2, at the end of which the TCI gate is closed, trapping the word NIA in TS COUNT. When as the result of an Instruction using D27 or D28, Trigger D is stimulated during the Transfer, TCI signal is applied also for the succeed- ing minor cycle, m+T+3. During this second minor cycle, the successive digits of NIA emerge from TS COUNT, return to the TCI gate, and are inhibited; meanwhile, entering TS COUNT are the digits of the word stored in m.c. m+T+3 of DL"N", which will be called "NIB". When TCI ends, therefore, the word trapped in TS COUNT is not NIA but NIB. An Instruction which transfers a number to D28, thus has the function of choosing between two possible Instructions to succeed it. If the word being transferred is zero, the next Instruction is NIA, the word stored in DL"N", m.c. m+T+2; if the word transferred is non-zero, the next Instruction is NIB, the word stored In DL"N", m.c. m+T+3. For instance, the Instruction "16-28" will be followed by different succeeding Instruc- tions depending on whether or not the number in TS16 is zero. PRECAUTIONS It is intended that the effect of an Instruction which stimulates Trigger D shall be simply to add one to the effective value of the Timing number, as far as it concerns the selection of the next Instruction. In other words, NIB is to be taken as the next Instruction, and NIA is to be completely ignored. However, NIA actually enters TS COUNT, and emerges from it, in m.c. m+T+3, into the circuits which interpret Instructions and generate the required signals. In order to achieve the required result, some special precautions must be taken to ensure that no part of NS-y-37/11-57

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NIA is obeyed as an Instruction as it emerges from TS COUNT. During m.c. m+T+3, the successive digits of NIB are flowing from the NIS gate of DL"N" along IHW to the TCI gate, and entering TS COUNT. If the digits of NIA, at that time emerging at "N", were permitted to affect the IS triggers, they might alter the selection of the NIS gate, replacing part of NIB with the word in the corresponding minor cycle of a different Delay Line. The fact that TCI signal is still present is therefore used to inhibit the digits at "N" before they can be used to generate the IS signal (see Figure 6.6). If the Go digit of NIA were "1", it would stimulate Trigger GO, in spite of the fact that NIB might be a Stop Instruction. If the Wait Number of NIA were zero, a pulse would emerge at "C" during m.c. m+T+3, which would tend to stimulate Trigger R. Both these points are met by the fact that, since TCI is still on, Trigger GO is cleared at Q16 in that minor cycle. (see Figure 6.14). This leaves NIB to restimulate GO, or not, depending on the value of its Go digit; it also prevents the pulse (if any) at "C" from stimulating Trigger R, since this signal can occur only at P22 time, when Trigger GO will be off. Again, the P16 digits of NIA and NIB might be "1" and "0" respective- ly; Trigger S would be stimulated by NIA passing through Control, and must be cleared somehow to allow NIB to operate properly. This is done by the CIS clearing connection to Trigger S (Figure 6.10) which leaves Trigger S always off at the end of TCI signal, that is at the moment when the Instruction actually to be obeyed has finished entering TS COUNT; this Instruction then sets Trigger S according to its own P16 digit. SELECTOR TREES The function of a Selector Tree has already been described. Any further explanation of the NIS Tree will be left for the Circuit Manual. Each of the other two Trees, however, really consists of two Selector Trees of this type: the HWE and TT connections are, in fact, more complex than has yet been shown, though their function has been accurately represented. SOURCE SELECTOR TREES AND HWE The details of the HWE connections and the two Source Selector Trees are shown in Figure 6.18. The HWE points from the 32 Source gates, pre- viously shown as all connected together, are really connected in four groups of eight; the HWE points from S0 to S7 are connected to HWE0, those from S8 to S15 are connected to HWE1, those from S16 to S23 are connected to HWE2, and those from S24 to S31 are connected to HWE3. Similarly, the SC connections are also made in four groups of eight, these connection points being called SC0, SC1, SC2 and SC3. Of the five IS triggers corresponding to the Source number of the current Instruction, NS-y-37/11-57

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the first three are connected to the First Source Selector Tree, and the last two to the Master Source Selector Tree. Each of these Trees always gives an output signal on just one of its eight or four possible output lines, depending on the binary number represented by the signals supplied from the IS triggers. Each of the eight output lines from the first tree is connected to four Source gates, one in each group; thus HWE0, HWE1, HWE2 and HWE3 each carry a sequence of digits from one of the Sources in its group. Each is presented at one of four Master Source gates, one of which is opened by a signal from the second tree to release the corres- ponding signal into the main Highway. As an example, suppose the Source number in the current Instruction is 23, represented by the sequence of pulses 11101. The first three digits go to the first tree, giving a signal on the output line connected to S7, S15, S23 and S31. All these Source gates are opened, the signal from S7 (the words in DL7) appearing an HWE0, that from S15 (TS15) on HWE1, that from S23 (TS14 χ 2) an HWE2, and that from S31 (ones) on HWE3. The last two digits of the Source number are applied to the second tree, which gives a signal on the output line connected to Master Source gate 2, allowing the pulses on HWE2 to pass to the main Highway. Thus the setting of the number "23" on the IS triggers carrying the Source digits releases the signal at Source gate 23 on to the main Highway, the same result as achieved by the simpler system shown before. The more complicated system is used because it gives more reliable operation in practice. However, there is now no single line carrying a signal which can truly be called "S23". In future the selector signal will be called, for example "S7(23)", since only the simultaneous application of signal at "S7" and at output "2" of the Master Scarce Tree will release the signal from "Source Gate 23" on to Highway. DESTINATION TREES AND TRANSTIM A typical Destination gate is shown in Figure 6.19, as a reminder; the dotted connections refer to storage positions, where the Destination gates act as changeover switches. The "TT" points of all 32 gates were previously shown joined together; in practice, however, these points are joined only in four groups of eight. The arrangement, similar to the HWE connections to Source gates, is shown in figure 6.20. The inputs from Triggers IS13 and IS14 determine to which of the lines TT0. TT1, TT2 and TT3 Transtim signal shall be routed when it appears. If the Destination number of the current Instruction is 13, for example, Destination Selection signals are applied to the Transtim gates of D5, D13, D21 and D29; when Transtim signal is applied, it is routed to the line TT1 and opens only the gate of D13. Again, the new notation will now be adopted of calling the Destination selection signal, for example, "D5(13)". NS-y-37/11-57

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PROGRAM DISPLAY Two special facilities are provided for testing new Programs. One of these is called Program Display; it involves connections to Control, Trigger PUNCH and the Output Staticiser (D29). The circuit is shown in Figure 6.21. Trigger H, which is stimulated by CIS at the moment when each new Instruction has finished entering TS COUNT and is about to start emerging at "J", is a special type of trigger which automatically clears itself a fixed time (in this case, about 40 microsec) after it has been stimulated. The return path through the 40 microsec delay has been inserted for logical completeness, and has no particular electronic equivalent. The signal from Trigger H covers the minor cycle while each Instruction first emerges from TS COUNT, and part of the next m.c. The digits covered in the second m.c., however, are identical with those in the first, since Trigger H clears itself before the second appearance at "J" of P16, the first digit affected by the Unit Subtractor. The output of gate "P" is thus a copy of each successive Instruction, just as it entered TS COUNT, with a second copy of the first few digits. Normally, this does not pass gate "Q", and has no effect on the operation. There is a key on the Control Duel labelled "Program Display"; if this key is down and the Stop Key is in the Augmented Stop position, a signal is applied at the point marked "PD". This signal has three imme- diate effects. Firstly, it stimulates Trigger PUNCH, so that cards run continuously through the Hollerith Punch; this provides a Single-Shot signal as each row of a card passes the punching station, causing succes- sive Instructions to be obeyed only in time with the successive rows (since we are at Augmented Stop). Secondly, it inhibits any words which might be sent to D29 by an Instruction from reaching the OS and being punched; such an Instruction is therefore "obeyed" in its turn, but has no practical effect. Finally, it sends to the OS the signal from gate "P", which consists of a copy of each successive Instruction in the order in which they are obeyed; the second copy of some of the digits has no effect, tending merely to restimulate those OS triggers put on by the first copy. The complete effect of the "Program Display" key is that the program is carried out normally, but at a speed determined by the Hollerith Punch. Instead of displaying or punching any results of the computation, however, all the Instructions are punched in the order in which they are obeyed. It is arranged that when the STOP Trigger comes on it inhibits the action of the Program Display Key. Thus when a Stopper is reached in the course of doing Program Display, the Punch stops and no further progress is possible until the Release Key is pressed and Program Display restimu- lated. REQUEST STOP (FUNCTION) The second special facility for testing new programs is called Request Stop. When in use, is causes the computer to stop automatically NS-y-37/11-57

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as soon as an instruction enters TS COUNT which has a previously specified Source, Destination or NIS number, or any combination of these. Different settings of keys, for example, will cause the computer to stop as soon as it reaches an instruction with NIS 5 (S and D irrelevant) or an instruction "13-27" (NIS irrelevant). The operation of Request Stop involves additional functions of the External Tree key and the 14 IS keys and three special Request Stop keys labelled "NIS", "S" and "D" respectively. Request Stop is brought into action by raising the External Tree key and pressing the appropriate selection of the three special keys; the selected NIS, Source and Destination numbers will be those currently set on the IS keys. Thus, if the IS keys are set at "5, 13-27", the relationship between the form of the stopping instruction and the setting of the Request Stop key is as follows ("n, 13-d", for instance, means that the computer will stop as soon as it reaches an instruction with Source number 13, independent of the NIS and Destination numbers):- Request Stop keys down Stops at first instruction of the form Source only n, 13 - d Destination only n, s - 27 NIS only 5, s - d Source and Destination n, 13 - 27 NIS and Source 5, 13 - d NIS and Destination 5, s - 27 All three 5, 13 - 27 Thus, if one key is already down, pressing a second and a third makes the computer less likely to stop, since it increases the speciality of the instruction form needed to stop it. If none of the three Request Stop keys is down, the computer will not stop, even though the External Tree key is in the up position. It world perhaps be more correct to describe the computer as "inter- locked" rather than "stopped" by Request Stop. Trigger GO remains on, and action is suspended only so long as conditions for stopping are maintained; if the relevant IS keys are moved, or External Tree key returned to normal, the computer immediately proceeds. REQUEST STOP (MECHANISM) Request Stop works by injecting a signal at the CMI input to Control NS-y-37/11-57

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whenever conditions for stopping are fulfilled. While the signal is present, Trigger R is stimulated every major cycle and cleared 6 microsec later at PbD6 time, before Trigger TT or Trigger Q has had time to come on. The instruction in suspense is thus not obeyed until the Request Stop conditions are removed. However, it will be seen in the next chapter that the Destination Triggers functions are operated by PbD6, and not by TT. It is therefore unsound to interlock on an instruction with Destina- tion number 24 (Destination Triggers), since the instruction would be repeatedly obeyed, once every major cycle, while waiting in TS COUNT. The connections for Request Stop are Shown in Figure 6.22. If External Tree key is up and one or more of the Request Stop keys down, a signal is injected at the CMI input to Control unless it is inhibited by non-fulfilment of the relevant condition. The state of the IS triggers is sampled by a set of 14 not-equivalent gates; each of these gives out a signal if the corresponding IS trigger and key are in opposite states. The first three of these signals are combined in a one-gate, which thus gives a signal at point N unless the instruction in TS COUNT has a NIS number equal to that set on the first three IS keys. Similarly, there is a signal at points S and D respectively unless the Source and Destination numbers in TS COUNT correspond with those on the IS keys. The three signals at points N, S and D are switched by their respec- tive Request Stop keys into a common one-gate, which thus gives a signal at point R if there is any discrepancy in the selected parts of the instruction between the word in TS COUNT and the IS keys. If the External Tree key is up and one or more of the three Request Stop keys is down, a signal is generated at Point S. This signal passes to the CMI input to Control unless it is inhibited by a signal at Point R. Thus, to sum up, a signal is injected at the CMI input to Control if, and only if, there is complete agreement between TS COUNT and the IS keys over the selected portions of the instruction word. The inhibiting action of a signal at the CMI input to Control has already been described in the paragraph on Control-Magnetics Interlock. COMPLETE DIAGRAM OF CONTROL Figure 6.23 gives a complete logical diagram of Control excluding the IS Triggers, the Selector Trees, and the detailed Request Stop arrangements. NS-y-37/11-57

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DESTINATION TRIGGERS

D24 is used for various assorted operations about the Machine which have in common only the fact that none of these operations requires the transfer of information through the Highway. The connections are shown in Figure 7.1. In contrast with all other Destination Gates, D24 operates, not on Transtim, but on the brief PbD6 signal which occurs shortly before the start of Transtim. The object of this is to ensure that, in spite of any accidental circuit delays, Triggers MULT and DIV are always brought on at least by the beginning of the minor cycle in which the Instruction stimulating them is officially obeyed. Since Transtim is not used, a dummy D24 Destination Gate is inserted to provide an alternative path for the Transtim signal, which would otherwise divide itself among other Destination Gates (see circuit manual for precise operation of Trees and Gates). Which of the twelve possible operations is required is specified by the Source number of the Instruction, that is by the setting of the IS Triggers corresponding to P5, P6, P7 and P8 (P9 is not used, since the twelve operations required can all be accommodated within the first 16 Source numbers). The PbD6 signal gated by D24 is first routed to one or other of two groups of 2-gates, according to the state of IS8, to the group of eight numbered 0 to 7 if the P8 digit is “0” and to the group of four numbered 8, 9, 10 and 12 if the P8 digit is “1”. The Instruction "11-24" is not used because it could cause complications with Control- Magnetics Interlock if a Magnetic operation were in progress at the time (see the chapter on Magnetics). Within each of the two groups of 2-gates, selection is done by con- nections from the First Source Tree. For example, if the Instruction were “18-24”, the First Source Tree would give signal only on its “O” output line, not on the other seven; the PbD6 signal would be routed first to the group of four 2-gates, since the P8 digit is “1”, and then by the Tree output to Gate 8 to clear the OS. The twelve functions of Destination Triggers are set out below: Instruction Effect 0 – 24 Stim MULT 1 – 24 Stim DIV NS-y-37/11-57

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These initiate multiplication and division as already partially explained 2 – 24 TIL Discrim When reading or punching, it is often desirable to distinguish the last row on a card from its predecessors; this row is therefore marked by a special signal called TIL (twelfth impulse line) which is issued by the Reader or Punch respectively for a period covering the time when the twelfth row is under the reading brushes or punching knives. To achieve the object of following a different course of action after the twelfth row from that pursued after the others this TIL signal must be connected to D28 which discriminates between zero and non-zero numbers. Since TIL is not wanted for any purpose other than connecting to D28 this connec- tion is made automatically by the Instruction "2-24"; this avoids the necessity of allocating a special Source number to TIL. 3 – 24 Stim TCA 4 - 24 Clear TCB 5 – 24 Stim TCB TCA and TCB are trigger circuits which modify the action of certain Sources and Destinations; they will be described subsequently 6 – 24 Clear ALARUM 7 – 24 Stim ALARUM Many programs incorporate arithmetic checks on their own operation; the failure of such a check is most conveniently indicated by operating the Alarum. This sounds a buzzer and lights a special red lamp on the Control Panel 8 – 24 Clear OS It is necessary to clear the OS between displaying successive words, since otherwise all those lamps would remain lit which had corresponded with a digit “1” in any of the words displayed. 9 – 24 Clear PUNCH and READ 10 – 24 Stim PUNCH 12 – 24 Stim READ NS-y-37/11-57

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LOGICAL OPERATIONS UNIT

Associated with TS14 and TS15 are four extra Sources, S23 to S26. If one of these Sources is selected, the digits released onto the Highway will represent some special function of the numbers in either one or both of the two TSs. In two cases, the output depends only on TS14; in the other two, it depends on both TS14 and TS15. S23: TS14 χ 2 S23 gives the number in TS14 divided by 2. If the successive digits in TS14 are A1, A2, . . . A32, then the digits at S23 will be A2, A3, . . . A31, A32, A32. This gives an answer true in the Signed convention explained in the notes an the Representation of Numbers in the DEUCE Programming Manual. S24: TS14 x 2 S24 gives the number in TS14 multiplied by 2. The successive digits at S24 are 0, A1, A2, . . . A31. S25: TS14 & TS15 The word available at S25 has a “1” only in those digits which are “1” in both TSs, and "0" in all other digits. S26: T814 T815 The word at S26 has a “1” in those digits which are different in the Two TSs, and a "0" in those which are the same. These functions are generated in the Logical Operations Unit, which is inserted in the circulation path of TS14 and connected with TS15 as shown in Figure 8. 1. The normal Sources and Destinations of the TSs have been drawn as boxes to simplify the diagram. Within the Unit, the pulses at A and C are combined to generate the functions; and A is connected to B through a unit delay. The Delay element of TS14 is made 1 microsec shorter than usual, so that both TSs act as normal storage positions, whether or not the special Sources are being used. A simplified version of Logical Operations Unit itself is shown in Figure 8.2. The two functions of the number in TS14 are generated indep- endently, so that the diagram breaks up into three quite simple parts. At the time marked by, say. the Q5 pulse, the digit at B will be (by definition) A5; that at A will be A6, and that at D A4. for 31 of the NS-y-37/11-57

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32 digits, the signals at A and D pass to the respective Source gates to give the functions TS14 χ 2 and TS14 x 2. At Q32 time, the digit at A is A1; this is inhibited by the Q32 signal, and replaced with a second copy of A32. At Q1 time, the digit at D is A32; this is inhibited by the Q1 signal. The functions TS14 & TS15 and TS14 TS15 are generated by apply- ing the digits in TS14 and TS15 to the inputs of a composite gate. Certain complications are introduced to avoid the electronically undesirable operations of gating together and delaying narrow pulses. The Logical Operations Unit is shown more accurately in Figure 8.3; it includes a "J-N Widener” circuit, for which the waveform are shown; this circuit consists simply of a trigger, stimulated by J14 and cleared by N14, which thus gives a widened version of the word in TS14. The widened digits produced last from clock-pulse to clock-pulse; in order to gate clock-pulses and digits from J15 or N15, this signal must be delayed by half a microsec (actually, slightly more than half a microsec, to allow for the fact that the widener trigger works from the front edge of the clock-pulses). It is then gated with clock-pulses and returned to K14; it will be seen that the successive digits at J14 appear at K14 one micro- sec later. The widener and half microsec delay thus have the effect of the one microsec delay shown between J14 and K14 in the simplified diagram and also give a widened version of the K14 signal for use in generating TS14 x 2, 14 & 15 and 14 15. The generation of TS14 χ 2 is identical with that shown in the simplified diagram. The only change in TS14 x 2 is that the widened K14 signal is delayed and then clocked; this avoids the necessity of passing a narrow pulse through a delay network, which is necessarily a rather unreliable operation. The gates for 14 & 15 and 14 15 combine the widened K14 signal with the narrow J15 and N15 signals; this both avoids the gating together of two narrow signals and gives a narrow output which does not need a further clock-pulse gate. A little simplification is achieved by using N15 as well as J15. NS-y-37/11-57

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THE ADDER

The Adder unit, which, it will be remembered, has two inputs and one output, may be regarded as a sort of gate. The pulses of signal at the output always represent the binary sum of the two numbers applied to the inputs. A particular output digit depends not only on the two current input digits but also on what has gone before, since provision must be made for "carry". Only the basic principles of the Adder's operation will be described at first, since the actual set-up is confused by considerations of timing. The final sum is produced in two steps. First, the two current input digits are combined to generate an intermediate current sum digit and a carry digit; the intermediate current sum digit is then added to the carry from the previous digit to form the final output. Each of these steps is carried out by a Composite Gate; It will be seen that the two outputs of such a gate represent respectively the sum and carry digits corresponding to its two inputs, according to the four rules of binary addition. 0 + 0 = 0 and 0 to carry 0 + 1 = 1 + 0 = 1 and 0 to carry 1 + 1 = 0 and 1 to carry The sum digit is "1" only if the two inputs are different; the carry digit is "1" only if both input digits are "1". The other main component of the Adder is a Unit Delay, which takes the carry digit from the first gate and presents it at the second just in time to be added to the sum produced by the succeeding pair of input digits. The connections are shown in Figure 9.1. The second step of addition may produce, as well as a final sum digit, a second carry which must again be added to the next digit. This would necessitate a third composite gate, were it not for the fact that the first and second carry digits (at E and F respectively) can never be "1" simultaneously. For if E is "1", A and B are both "1", D is "0", and F is "0" for either value of H. The output from F can therefore be brought back to the input of the original delay with no risk of confusion. An example is given of the successive digits at various points for a typical addition. NS-y-37/11-57

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ROUND CARRY SUPPRESSION The signed Convention described in the notes on the Representation of Numbers requires the suppression of any carry from the 32nd digit of an addition. This is achieved by an Inhibitor-Gate at the input to the carry delay. The inhibiting signal is Q32, which prevents any input to the second Composite Gate during the first digit of the next word. SUBTRACTION A little extra equipment in the Adder Unit enables it to be used at will for either addition or subtraction. The adder has, in fact, three inputs, as shown in Figure 9.2; one input being connected to D25, one to D26 and the third being the circulation path of TS13. A number trans- ferred to D26 is subtracted from the former contents of TS13. The necessary modifications to the Adder Unit are shown in Figure 9.3. The process of subtracting a number "n" is really that of adding "-n". The pulses representing "-n" are generated by interchanging the "0"s and "1"s in the representation of "n", and adding 1 to the result. These steps are taken separately; the number is negated before entering the adding part of the Unit, and 1 is added by a modification of the Round Carry Suppression mechanism. D25 applies the number on HWL to the adder, which operates just as before; the digit carried round from the 32nd digit to the first digit of the next word is always zero. D26 applies the negated version of HWL to the adder; in this case, gate A passes a Q32 signal to the input of the unit delay, so that the digit carried round from the 32nd digit to the first digit of the next word is always one. This is equivalent to adding "1" to the answer for every minor cycle that D26 Destination gate is open, in other words for every word sent to the subtractor The transfer "14-26 ( 3 m.c.)" subtracts three times the number in TS14 from the number in TS13. The operation in detail is that S14 and D26 are selected so that repeated copies of the word in TS14 appear at HWL. Transtim signal is now applied for three successive minor cycles, during which three negated copies of the number are added to the contents of TS13. At the end of each of these minor cycles, a "carry" is forced from the 32nd digit, with the total result that the number "1" is added into TS13 three times, completing the desired effect. A commonly used transfer is "13-25", which doubles the number in TS13 by adding it to itself. This transfer would not work with the Adder con- nections as shown in Figure 9.4, since the Highway connection, shown by the dotted line, would effectively short-circuit the Adder Unit. In general, an arithmetic unit incorporating special Destinations must be connected between the Destination and the delay element of a storage position, while one incorporating Special Sources must be connected bet- ween the delay element and the Source. NS-y-37/11-57

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WIDENERS There are two respects in which this simple adder-subtractor in inade- quate, In the first place. as has already been pointed out, it is not practicable to gate together two signals each of which consists of narrow pulses. For this reason, a widener is inserted in both leads into the adder itself, the one carrying HWL Signal and the one carrying the circu- lation path of TS13. As a result, the word of wide signal entering the adder now lasts from P1 to P1, not from a point midway between P32 and P1. To allow for this, the signals from D25 and D26 destination gates are both delayed by about ½ microsec before being gated with the widened HWL signal (the actual theoretical delay is 0.35 microsec, since wideners work off the front edge of a narrow pulse, not the centre of it). All pulses are now 1 microsec wide and last from clock-pulse to clock-pulse; this is rather inconvenient, since such wide pulses can never be gated with clock- pulses; a further delay of about 0.5 microsec is therefore introduced in each lead (the actual value is 0.35 microsec, to allow for delays in circuitry and the difference in timing between HWL signal Pad clock- pulses). The input system is shown in Figure 9.5. After all this, the digits actually enter the adder 1 microsec later than normal timing. For instance, the sixth digit of a word enters the adding circuits and is dealt with during Q7 time. In particular, the 32nd digit is treated during Q1 time; since it is from this digit that carry mast be suppressed, the round carry suppression must be worked by Q1, not by Q32. CARRY TRIGGER The other inadequacy of the simple system is best illustrated by an example. Suppose that TS13 is initially full of ones and that P1 is sent to D25 for one minor cycle. All the ones in TS13 should change to zeros, since there is a carry from each digit which combines with the next "1" in TS13 to generate a zero digit and a unit carry digit. Let us consider this process in more detail by referring to Figure 9.5 and setting out the digits appearing at each point of the diagram in successive microsecs (allowance is made for the unit delay introduced by the wideners). Time Q2 Q3 Q4 Q5 ---------- Q31 Q32 Ql Q2 A 1 0 0 0 0 0 0 0 B 1 1 1 1 1 1 1 1 D 0 1 1 1 1 1 1 1 E 1 0 0 0 0 0 0 0 G 1 1 1 1 1 1 1 0 H 0 1 1 1 1 1 1 0 F 0 1 1 1 1 1 1 0 C 0 0 0 0 0 0 0 0 NS-y-37/11-57

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The pulse at G during Q2 time appears at H in Q3 time and combines with the pulse at D to generate a pulse at F (also in Q3 time) which, of course, also appears at G. In effect, the pulse from G has passed through the unit delay and reappeared at G, and this process is repeated 30 times. In the simple system so far described, an error of 3% in the length of the 1 microsec delay network would introduce a cumulative delay of 1 microsec over the 32 microsec of the process, and lose a whole digit in the timing. Furthermore, the pulse would be liable to considerable distortion during its 31 passages round the loop. The example quoted is, of course, the extreme case, but the effects would also be present to a lesser extent in cases of shorter lengths of carry. The problem is similar to that of a pulse repeatedly circulating in a delay line storage location, and similar measures are taken to solve it, The wide pulse is gated with a clock-pulse to locate its timing and a new wide pulse is generated from the resulting narrow signal in order to restore its shape, The trigger which generates this wide pulse is called the Carry Trigger (not to be confused with the Carry Trigger in Control. which is quite different in function). The connections to the Carry Trigger are shown in Figure 9.6. Every Clock-pulse goes to one or other of the inputs of the Trigger, deter- mining its state for the next microsec. In the microsec from P1 to P2, the trigger is on if a subtraction is taking place and off otherwise; in the other 31 microsec periods, the trigger mirrors the signal from G, but is ½ microsec later and is corrected in shape and timing. The signal from the trigger is taken through a ½ microsec delay to correct its timing and to complete the 1 microsec delay wanted for the logical operation. The output of the Carry Trigger thus at all times represents the required lower input to the second composite gate. The complete adder system is shown in Figure 9.7. It will be observed that the undelayed output from D26 gate is taken to operate the carry mechanism; this means that in the case of subtraction the extra "1" which has to be added is inserted at the beginning of each minor cycle of operation, not at the end. This is irrelevant in the case under discussion, that of subtraction into TS13; it will become quite important, however. when we come to consider subtraction into DS21. NS-y-37/11-57

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THE MULTIPLIER-DIVIDER UNIT

The Multiplier-Divider Unit contains circuits for performing five arithmetic operations associated either with DS21 or jointly with DS21 and TS16; a sixth operation, associated with TS16 but performed in another unit, will for convenience also be described in this section. The five operations are closely linked, since some of the equipment in the Unit is used in all five of them and quite a lot of it in four. The five facilities are, viz., shift down, addition and subtraction in DS21, multiplication and division. The first three of these are modified in operation by a trigger called TCB which is operated through Destination Triggers; when TCB is off, they perform double-length arithmetic, treating the digits in DS21 as a single 64-digit number; when TCB is on, they perform single-length arithmetic, treating the digits in DS21 as two quite separate 32-digit numbers. All but the first of the facilities uses an adder-subtractor circuit, similar to the one associated with TS13 but somewhat more complicated. The sixth operation is the minor cycle shift facility associated with DL1O and TS16 and controlled by TCA, another trigger operated through Destination Triggers. MINOR CYCLE SHIFT The Minor Cycle Shift facility is the simplest and will be described first. The connections are shown in Figure 10.1. While TCA is off. TS16 and DL10 behave as normal storage positions, When TCA has been stimulated by the Instruction "13-24", the circulation path Of TS16 is broken; any digits sent to D16 are immediately lost and the storage capacity of TS16 is destroyed. DL1O continues to behave normally except that a copy of the digits emerging from its delay are sent to the input of the delay of TS16 and pass through this delay to S16. S16 thus gives just the same output as S10, except that every digit occurs 32 microsec later. In this condition. the Instruction "16-10 (m.c.5)" replaces the word in 105, with a copy of that in 104, leaving two copies of the latter. The Instruction "16-10(32 m.c.)" replaces the word in every m.c. of DL10 with that previously stored in the preceding m.c. In other words, the whole contents of DL10 are shifted round by one minor cycle; this is the main justification for TCA's existence. When some arithmetic process has to be carried out in turn on each of several numbers, these numbers are commonly stored sequentially in DL10 and shifted round by one minor cycle before each repetition of the arithmetic Instructions. The delay of 0.1 microsec between J10 and H16 is to compensate for the fact that digits at J are at HWE time and those at H are at HWL time; by virtue of this delay, the digits arriving at the Clock-Pulse gate in TS16 have the same timing whether they reached H16 from G16 or from J10. NS-y-37/11-57

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There is no point in clearing TCA until TS16 is again to be used as a storage position. The only provision for clearing TCA is therefore an automatic one which works shortly before the beginning of any transfer to D16. It uses the PbD6 signal from Control gated with P27 and P28 as shown in Figure 7.1. TRIGGER ODD AND TCB It has been said that addition, subtraction mad shifting down may be performed either as single-length or as double-length operations. In double-length operation. a 64-digit number is always regarded as having its less significant half in an oven numbered minor cycle, so that it runs in the direction of increasing significance from P1 (even) to P32 (odd); this convention also applies to the double-length product of two single- length factors produced by the automatic Multiplier. Provision in the circuits for the distinction between single-length and double-length working need be concerned only with arithmetic opera- tions; it is irrelevant, for example, whether a block of 64 digits trans- ferred from one storage location to another represents two 32-digits numbers, one 64-digit number or half of a 128-digit number. Furthermore, this distinction is necessary only because special treatment may be required for the first or last digit of a number; it will be remembered that in the Logical Operations Unit S23(TS14 χ 2) and S24(TS14 x 2) required special treatment respectively for the P32 and P1 digits. Figure 10.2 shows the points at which such special treatment would be required in single-length and double-length operation or, to put it another way, the waveforms of the signals which would be required to control such special treatment. We see that two signal lines are required, each capable of being supplied with two alternative signal patterns; one line (called M1) must carry the Q1 pulse from every even m.c. for double-length arithmetic and every Q1 for single-length; the other (called M0) must carry odd Q32's only for double-length and all Q32 for single-length. The arrangements for producing these signals are shown in Figure 10.3 TCB is stimulated by the Instruction "5-24" and cleared by "4-24"; it is off for double-length arithmetic and on for single-length. The distinction between odd and even minor cycles is maintained by a trigger called Trigger ODD which is arranged to be on and off in alternate minor cycles, changing its state at every P32 time. It achieves this by directing the P32 signals to its own inputs in such a my that if it is off during any minor cycle it is put on by the P32 at the end of it and vice versa. The delay shown as 15 microsec need not be accurate, anything from 2 microsec to 30 microsec would do; the object is to provide a margin of safety between the timing of the P32 pulses and the Trigger ODD output with which they are combined to operate Trigger ODD. The convention is adopted that the minor cycles for which Trigger ODD NS-y-37/11-57

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is on are the odd-numbered ones (hence the name). The relationship bet- ween this oddness and the actual minor cycle numbering must be established separately for each program run into the Machine; this is one function of the Initial Card which is found in front of most programs (the other function is to clear TCB so that the program starts with a Machine in a completely standard condition). With this convention, the delayed signal from Trigger ODD covers the end of each odd m.c. and the beginning of each even one. From this, and the figure, it is clear that with TCB off M0 gives odd Q32 and M1 gives even Q1. Stimulating TCB fills the gaps left by Trigger ODD, so that M0 and M1 just give Q32 and Q1 respectively. M0 and M1 are thus as specified; the problem remains of using them. The even P1 and odd P1 generated by the gate at the bottom of the figure are used for various purposes about the Unit; they are shown here for the sake Of completeness. SHIFTING DOWN (DOUBLE-LENGTH) S22 gives DS21 ÷ 2. It will be remembered that in the Signed conven- tion division by two is represented by shifting every digit down one, dropping the bottom one, and filling the vacant space at the top of the number with a copy of what was there before; there are then two copies of this top digit, one in the top position and one next to it. The only question is whether this "top digit" is odd P32 only (double-length working) or both P32 (single-length working). The digits in DS21 and the corresponding digits required from S22 are:- even minor cycle odd minor cycle DS21 A1 A2 A3 ..... A30 A31 A32 B1 B2 ..... B30 B31 B32 S22 A2 A3 A4 ..... A31 A32 X B2 B3 ..... B31 B32 B22 If TCB is off, the "X" shown beneath A32 should be B1; if TCB is on, X should be A32. The gating by which this is achieved is shown in Figure 10.4. It is almost identical with the gating for generating TS14 ÷ 2 for S23, and should need no further exploration. With one Instruction, shifts down of up to 16 places may be performed either on a 64-digit number (TCB off) or on two 32-digit numbers simult- aneously (TCB on). Only 16 place shifts are Possible because 32 m.c. is the maximum length of transfer Fad it takes 2 m.c. to shift the whole 64 digits by one Place. The Instruction for shifting a double-length number by n Places is "22-21 (2n m.c. e,o)", implying that transfer must start in an even m.c. and end in an odd one. The reason for this will be explained by reference to an attempted shift of one place by the Instruc- tion "22-21 (2 m.c. o,e)". The few centre digits are shown below, initially, NS-y-37/11-57

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after transfer for the odd m.c., and after subsequent transfer for the even m.c. initially A30 A31 A32 B1 B2 B3 after odd m.c. transfer A30 A31 A32 B2 B3 B4 finally A31 A32 B2 B2 B3 B4 It will be seen that B1 has been lost and replaced with an illegitimate copy of B2. For more places of shift attempted by the Instruction "22-21 (2n m.c.o,e)" there will be a block of n digits in the middle which has been shifted down one place too many, exterminating the digit in front of them and duplicating the digit behind them. In this diagram, the circuits for the other arithmetic functions are shown in a block; in future diagrams, the S22 arrangements will be similarly abbreviated. THE LONG ACCUMULATOR

Words sent to D22 are added to the contents of DS21; those sent to D23 are subtracted. The arrangements are shown, with deceptive simplicity, in Figure 10.5. The M1 connection is for round carry suppression as performed by the Q1 input it the TS13 adder. (It will be remembered that the wideners at the input to the adder introduce a delay of 1 microsec, so that Q1 coincides with the top digit of the input, not the bottom). This again allows TCB to stipulate either double-length or single-length working. As in the case of TS13, subtraction is performed by negating the digits applied to the adder input and modifying the round-carry suppres- sion mechanism to add a "1" at the beginning of every word (that is, every single-length or double-length word, as the case my be). So far, very simple; in fact the system is now adequate for single-length working or for complete double-length working in which every transfer is for 2n m.c. (e,0). One complication arises when we consider the effect of the Instruction, "15-233" when TCB is off. (It will be remembered that to avoid confusion between "0" and "odd" the minor cycles of a DS are numbered 2 and 3, not 0 and 1). The intention is to subtract a single-length number from the top half of the double-length number in DS21; this requires provision both for negating the number at the input to the adder and for adding a "1" at the beginning of the number. The negating happens all right in the usual way, but since (with TCB off) M1 gives no pulse at the beginning of an odd minor cycle the "1" will not be added unless we do something about it. The action taken is to modify the operation of M1 so that it gives a Q1 pulse, not only in every minor cycle when TCB is on and in every even m.c. when TCB is off, but also in the first m.c. of any transfer to D23, even though this may be an odd m.c. with TCB off. Having decided this, NS-y-37/11-57

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the extra connections are very simple, as shown in Figure 10.6; the 2- gate leading to M1 is opened either if trigger ODD was on in the previous m.c. or if TCB is on, or if a subtraction (i.e. a transfer to D23) has just started, or any two or all three of these. It my appear that the action of M0 has also been affected, but this is not so; the beginning pulse from D23 Destination gate happens at the beginning of a minor cycle, and can never coincide with a Q32. A second complication is illustrated by the Instruction "15-232" when TCB is off add TS15 contains a positive number which we will call "x". The object is to subtract this single-length positive number from the bottom half of the double-length number is DS21. This time, both the negating and the addition of "1" are provided for, but trouble now occurs at the top end of the single-length number. It was pointed out in the notes on "Representation of Numbers" that the negation of a 32-digit positive number "x" actually represented 232 -x-l; adding "1" gives 232-x. Thus our subtracting process is equivalent to subtracting x and adding 232 which is 1 at the bottom of the top half of the double-length number. An example will illustrate the very deleterious effect of this. We will suppose that DS21 contains "-5" in double-length form, which is 264-5 or, putting it another way, 232-5 in the even m.c. and all ones in the odd m.c. TS15 contains "3", so that the subtraction should produce "-8" in double-length form. even m.c. odd m.c. TS15 1 1 0 0 0 ......0 ~TS15 + 1 1 0 1 1 1 ......1 DS21 1 1 0 1 1 ......1 1 1 ...... 1 Result 0 0 0 1 1 ......1 0 0 ...... 0 So that the result of subtracting a small positive number from a small negative number is a middle-sized positive number in double-length notation. It will be observed that if TS15 had contained "-3" in single-length notation (i.e. 232-3), everything would have worked splendidly, giving the correct answer 264-2 = (264-5)-(-3). Similarly, on the system so far described, adding a positive number by D22 would give the wanted result while adding a negative number would also add a spurious "1" into the top half. (We are still concerned with transfers in the even m.c. only, with TCB off). Any amendment of the system to correct these errors mast therefore come into operation only when a positive number is being subtracted or a negative number added, add not otherwise, and must have the effect of subtracting "1" to the top half. This is achieved by Trigger X, shown in NS-y-37/11-57

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Figure 10.7, which comes on in the required circumstances for just one m.c. and in effect injects a sequence of 32 "1"s into the adder circuit. Figure 10.7 also shows a little more of the adder input arrangements. The timing is complicated by the difference in timing between CP and HWL; this leads in practice to certain modifications which will be postponed until the complete MULT-DIV diagram is given. Trigger X is attached to the adder input after the point where using D23 causes the HWL signal to be negated. At this point, the single-length number being added appears negative if either a negative number is being sent to D22 or a positive one to D23, and it is in just these circumstances that assistance from Trigger X is required. In the length signed signed notation. a number is negative if its 32nd digit is a "1" and positive otherwise. Trigger X must be stimulated only if several conditions hold simult- aneously; first a transfer to D22 or D23 must have just ended; secondly, it must have ended with an even minor cycle; thirdly, TCB must be off; fourthly the even P32 digit entering the adder circuit must be a "1". The first condition is catered for by the end element connection from D22 and D23 Destination Gates; the second and third are taken care of by the M1 inhibiting connection which prevents stimulation of Trigger X at the end of any odd m.c. and at the end of any m.c. if TCB is on; the fourth is realised by the confection from the adder input (this also ensures that if Trigger X is not put on during Q1 of the relevant m.c. it will not be put on at all, since it Trigger X is off signal here will cease by Q2 time). Trigger X is cleared by even P1, so that it remains on, if stimulated, for just one m.c. as required. The system thus fills out to double length any single-length number added or subtracted into the bottom half of a double-length number. This may appear a little officious, particularly as the effect could have been achieved by programming and may in some circum- stances be unwelcome. However, the distinction between "contracting in" and "contracting out" is purely one of emphasis; the present arrangement was adopted because it was thought that true double length working would be more often required then not. AUTOMATIC MULTIPLIER To perform a multiplication, the multiplicand is first sent to TS16, the multiplier to DS213 and DS212 is cleared. Trigger MULT is then stimulated through Destination Triggers by the Instruction "0-24". After 65 minor cycles, multiplication is complete and Trigger MULT automatically clears itself. The result is that the 64-digit product of the two 32- digit factors is now In D21; the multiplier has been lost, but the multiplicand remains in TS16. The Multiplier treats the factors as un- signed positive numbers, so that a correction is required to the product to produce the effect of multiplication in the Signed Convention. This NS-y-37/11-57

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will not be described here since it is a matter of programming rather than Machine design. ARITHMETIC PROCESS OF MULTIPLICATION The arithmetic process embodied in the Multiplier is quite straight- forward, but it will be described in detail to fix firmly the order in which the various steps are performed. As an illustration, we will con- sider the multiplication of two three-digit decimal numbers. 567 and 432, to give the six-digit product 244944. This product is built up as the culmination of a series of partial products which we will call p1, p2, etc. The normal layout for this work would be:- 567 b 432 a 2268 1701 1134 244944 c If the DEUCE were a decimal machine, its procedure would be as follows:- 567 b 432 a 2268 p1 = 4 x 567 = 2268 2268 shift up P1 1701 add 3 x 567 24381 p2 = 10 x p1 + 3 X 567 24381 shift up P2 1134 add 2 x 567 244944 p3 = 10 x p2 + 2 x 567 = c In this case, p3 is the final product. There is one important simplification in using binary arithmetic. This is that the digits of the multiplier are all "0" or "l" (and the multiplicand too, of course). The products 4 X 567, 3 x 567, 2 X 567 in the example are therefore replaced with either 0 x b or 1 X b. In other words, the increment added to the shifted p(r) to give p(r+l) is either zero or the multiplicand. The process may therefore be expressed in words mere or less as follows:- (a) Clear product register (b) if top digit of "a" is "1" add in "b" (otherwise, do not) (c) shift up partial product. (d) if second digit of "a" is "1" add in "b". NS-y-37/11-57

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(e) shift up partial product etc. (P) Shift UP partial product (q) if 31st digit of "a" is "1" add in "b". (r) shift up partial product (s) if 32nd (bottom) digit of "a" is "1" add in "b". (t) STOP The examination of successive digits of the multiplier is done, not by examining the contents of successive digit positions, but by shifting the multiplier up one place each step and always examining the top digit. The process is illustrated below for the multiplication of 14 by 13 in binary, using for convenience a 4-digit instead of a 32-digit word length and than producing an 8-digit product. (The most significant digit is on the left). MULTIPLIER (a) MULTIPLICAND (b) 1 1 0 1 1 1 1 0 | |digit examined PARTIAL PRODUCTS 1 1 0 1 top digit "1", add in b 1 1 1 0 pl (1)1 0 1 (shift) (1 1 1 0) 2nd digit "1", add in b 1 1 1 0 1 0 1 0 1 0 p2 (1 1)0 1 (shift) (1 0 1 0 1 0) 3rd digit "0", add in "0" 0 0 0 0 1 0 1 0 1 0 0 p3 (1 1 0)1 (shift) (1 0 1 0 1 0 0) 4th digit "1", add in b 1 1 1 0 1 0 1 1 0 1 1 0 p4 = c = 182 The shifted partial products are parenthesised because they do not occur in this form; the shifting and the adding of the next contribution happen simultaneously, so that only the successive partial products marked p1, p2, p3 and p4 are actually seen. NS-y-37/11-57

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The brackets around the top digits of the multiplier indicate those digits which have already made their contribution to the answer and are now no further use; it is convenient to exorcise these digits succes- sively as soon as they have been examined, so that at any stage only that part of the multiplier is stored which comprises those digits Still to be examined. At first sight, it seems that three storage positions are required, the first single-length to hold the multiplicand. the second single-length to hold what is left of the multiplier. and the third double-length to hold the growing partial product. However, examination shows that the functions of the second and third of these can be combined in one double- length storage position. Consider the situation when the r'th partial product has just been completed; this partial product has at most (32 + r) digits, stretching up from the bottom of an even minor cycle to include the bottom "r" digits of the odd minor cycle. At this Stage, r digits of the multiplier have been examined, leaving (32 - r) digits which are still wanted; there is just room to keep these at the top of the odd minor cycle of the DS in which the growing product is stored, since the total number of digits is always exactly 64. This system of keeping the multi- plier and the partial product in the same DS has the additional advantage that both have to be shifted up by one place at each stage of the multipli- cation; this can now be achieved in one go by the same shifting mechanism. The example given above will now be redrawn to show the arrangements of digits in DS21 at successive stages of the multiplication. The multi- plicand 14 or 1110, remains in TS16 throughout Initially. the multiplier is in DS213 and DS212 is cleared. The pro- cess begins with an odd minor cycle at the and of which the top digit of the multiplier emerges from the delay of DS21 and is examined. Since in the example this digit is a "1", TS16 is added into DS21 during the second (even) minor cycle of the process. In the third m.c. the shifted remains of the multiplier (the top digit has already been removes) emerge from DS21 and the new top digit is examined. From now on, the process proceeds by pairs of minor cycles, an oven m.c. followed by an odd one. In the even m.c., the bottom half of the partial product in shifted and TS16 added (or not added) into it. In the odd m.c., the top part of the partial product and the remains of the multiplier are shifted and the top digit of the multiplier examined to determine whether or not TS16 is to be added into DS21 on the next round. In the schematic below, a vertical line indicates the break between the waxing partial product and the waning multiplier. It will be remembered that the process starts with an odd m.c., so that the multiplier emerges from DS21 in the first m.c. of multiplication, not the second. NS-y-37/11-57

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DS212 DS213 P1 P2 P3 P4 P1 P2 P3 P4 | Initially 0 0 0 0 1 0 1 1 digit examined after 3 m.c. 0 1 1 1 0: 1 0 1 after 5 m.c. 0 1 0 1 0 1: 1 0 after 7 m.c. 0 0 1 0 1 0 1: 1 after 9 m.c. 0 1 1 0 1 1 0 1: For 32-digit numbers, the entire process takes 65 m.c. EQUIPMENT FOR MULTIPLICATION Figure 10.8 shows the multiplication arrangements. They perform, quite simply, according to the scheme just described. Trigger MULT is stimulated by the Instruction "0-24", which must always be obeyed in an odd minor cycle (rule), and thus comes on at the beginning of an odd minor cycle. After being on for 65 minor cycles, trigger MULT is auto- matically quenched, as will be described shortly. This period is exactly sufficient, since the process requires 2 m.c. (even followed by odd) to form each new partial product, preceded by 1 (odd) m.c. in which the initial multiplier is run through by itself so that its original top digit may be examined. While MULT is on, the contents of DS21 pass through gate A and through a unit delay which shifts them up by one place in every pair of minor cycles. Gate A has the dual function of removing the odd P32 digit from the circulation path and directing this digit to the input of Trigger Y. Trigger Y is thus stimulated right at the end of any odd m.c. in which the P32 digit emerging from DS21 is a "1"; it is cleared, if it has been so stimulated, after exactly one m.c. by a P1 (odd). Trigger Y is there- fore always off during odd minor cycles and is on only for those even minor cycles during multiplication which immediately follow odd minor cycles in which the digit of the multiplier being examined is a "1". The output of Trigger Y during a multiplication may be said to represent the digits of the multiplier in reverse order (P32 through to P1), each digit "1" being represented by a 32 microsec pulse of signal during an even m.c. followed by a 32 microsec gap during an odd m.c. This is illustrated in Figure 10.9 by an example. The output of Trigger Y is delayed by half a microsec so that the edges of signal come not at P32 time but midway between P32 and P1; the pulses of signal then cover exact whole even minor cycles. Furthermore, these minor cycles are just the ones in which the contents of TS16 are to NS-y-37/11-57

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be added in to the shifted partial product. All that is needed is to use the delayed Trigger Y signal to gate the signal from TS16 into the second input to the adder. The system now carries out exactly those operations necessary to accomplish multiplication according to the system set out above. One or two points of detail need clarification. For instance, wideners are inserted both in DS21 circulation path immediately after D21 and in the connection from TS16 to the Trigger Y gate; these, with their compensating delay networks, introduce a delay of 1 microsec each. The operation of Trigger Y must therefore be 1 microsec late, both as regards its input from DS21 and its output to gate TS16. A compensating 1 micro- sec must be shaved off the DS21 delay. The top multiplier digit is therefore picked out with Ml, not with M0, and Trigger Y is cleared with P1 (odd), not P32 (even). The output from TS16 to the Multiplier is taken from J and N; this enables the more reliable type of "on-off" widener to be used, though the widener from DS21 has to be of the less fortunate "self-clearing" variety. TCB must be off during multiplication for two reasons. First, the addition of TS16 into the shifted partial product may require carry from P32(e) to P1(o) and secondly the M1 signal which works gate A must operate only on the top digit of the multiplier at P1(e) and not on the 32nd digit of the partial product which comes at P1(o) time. To make sure of this, an additional clearing input to TCB is provided; this comes from trigger MULT through a beginning element; TCB is thus automatically cleared (if it is on) at the start of any multiplication. Trigger MULT is stimulated through Destination Triggers, which uses the PbD6 signal coming from Control about 4 microsec before the start of Transtim. MULT thus comes on, not at the beginning of the odd m.c. in which it is stimulated, but at about P28 in the previous even m.c. This does not matter, since its only effect is to shift up a few of the zeros originally in DS212, and one zero looks very much like another. AUTOMATIC DIVIDER The arithmetic principles of the Divider are more confusing than those of the Multiplier. There are several ways of looking at the process, but comparison of these tends to make it still more incomprehensible. Only one line of approach will therefore be taken, starting from first principles. THEORY OF DIVISION In a process of division there are two input quantities, the Dividend (A) and the Divisor (B) and two output quantities, the Quotient (Q) and the Remainder (R). which are linked with the first two in certain relationships NS-y-37/11-57

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and are uniquely determined by them. In the simplest case, the relation- ships are :- A = B Q + R 0 < R < B For instance, if A = 214 and B = 9, then Q = 23 and R = 7, satisfying 214 = 9 x 23 + 7 and 0 < 7 < 9 Any apparatus which when given A and B will produce Q and R may be described as an automatic divider, however obscure the mechanism by which this result is achieved. This principle holds equally with the slightly more complicated division processes about to be described. It is often required to divide two numbers of about the same size and to produce the result to some specified number of decimal places. For instance, dividing 43 by 73 to two decimal places gives a quotient of 0.58 with a remainder of 0.66. This is verified by the relationship 43 = 73 x 0.58 + 0.66 corresponding to our first relationship above; in this case, however, there is no obvious equivalent to the second relationship. It is better to multiply both sides of the equation by 102, giving 43 x 102 = 73 x 58 + 66 where 0 < 66 < 73 or, more generally, for any division to P decimal places 1OP x A = BQ + R 0 < P < B It must be borne in mind that the Q and R obtained from this pair of relationships need dividing by l0P to give the true quotient and remainder, but this is just a matter of putting the decimal point in the right place. For present purposes, it is more convenient to treat A, B, Q and R all as integers and to say, if we wish to be pedantic, not that "Q is the quo- tient" but that "Q represents the quotient to P decimal places". In order to calculate a quotient to several decimal places it is normal to obtain it one digit at a time, whether the work is being done on paper, on a desk calculating machine, by program in a computer or auto- NS-y-37/11-57

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matically in a computer. The arithmetic principles are the same in all cases; to calculate each digit, the remainder left after the previous digit is taken as dividend. For example, the division of 43 by 73 to six decimal places is really carried out as in the following scheme: 10 x 43 = 5 x 73 + 65 10 x 65 = 8 x 73 + 66 so that 102 x 43 = 58 x 73 + 66 10 x 66 = 9 x 73 + 3 103 x 43 = 589 x 73 + 3 10 x 3 = 0 x 73 + 30 104 x 43 = 5890 x 73 + 30 10 x 30 = 4 x 73 + 8 105 x 43 = 58904 x 73 + 8 l0 x 8 = 1 x 73 + 7 106 x 43 = 589041 x 73 + 7 This may be expressed algebraically by writing Q1, Q2, etc., for the quotient being built up and R1, R2, etc. for the successive remainders. We then have:- 10 x A = Q1 B + R1 where 0 < R < B for all R 10 x R1 =(Q2 - 10Q1) B + R2 or 102 A = Q2 B + R2 10 x R2 =(Q3 - 1OQ2) B + R3 or 103 A = Q = Q3 B + R3 etc. 10 x R5 =(Q6 - IOQ5) B + R6 or 106 A = Q6 B + R6 The quantities in brackets are the successive single digits which have to be stuck on the end of each partial quotient to turn it into the next. So far, we have always stipulated that a remainder must be positive, but this is not really necessary, particularly in the intermediate stages. Sometimes it is more convenient or more accurate to allow remainders of either sign and always to aim at the smallest absolute value of remainder. For instance, in the example above, dividing 43 by 73 to two decimal places gave Q = 58 and R = 66. It might be better to have a system which gave Q = 59 and R = -7. It is then still true that 102 x 43 = 59 x 73 + (-7) but not that 0 < -7 < 73 NS-y-37/11-57

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In general, we now write 10P x A = B Q + R B B | - - < R < - | 2 2 | > A B B | or - - < R < - | 2 2 | It does not usually matter much which of the alternative forms of A is taken, but a mechanical system will, of course, work either always to one or always to the other. That they sometimes give rise to different answers is demonstrated by the division of 3 by 4 to one decimal place, which gives Q = 8, R = -2 or Q = 7, R = 2 depending on which form of A is in force. This principle may be applied throughout the division process, not only to the final answer, and often effects economies. Suppose the example above of dividing 43 by 73 to six decimal places were performed on a hand- operated desk machine. As laid out above, the number of turns of the handle required would be 5 + 8 + 9 + 0 + 4 + 1 = 27. This could be reduced by rearranging the work as follows:- 43 = 1 x 73 + (-30) 10 x (-30) = (-4) x 73 + (-8) so that 10 x 43 = 6 x 73 - 8 10 x (-8) = (-1) x 73 + (-7) 102 x 43 = 59 x 73 - 7 10 x (-7) = (-1) x 73 + 3 103 x 43 = 589 x 73 + 3 10 x 3 = 0 x 73 + 30 104 x 43 = 5890 x 73 + 30 10 x 30 = 4 x 73 + 8 105 x 43 = 58904 x 73 + 8 10 x 8 = 1 x 73 + 7 106 x 43 = 589041 x 73 + 7 The total numbers of turns is now 1 + 4 + 1 + 1 + 0 + 4 + 1 = 12. This method of doing division on a desk calculating machine is often des- cribed as "short-cutting". It is more closely analogous to the operation of the DEUCE Divider than is the previous system in which only positive remainders were allowed. When we pass from decimal to binary arithmetic there is, as in the case of multiplication, a simplification from the fact that only the digits "0" and "1" are used. In the example immediately above, there is a choice of 11 operations at each stage; we may have to add or subtract 1, 2, 3, 4 or 5 times the divisor, or to do neither (see the stop which reads "10 x 3 = 0 x 73 + 30"). The corresponding choice in binary is only NS-y-37/11-57

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threefold; to add the divisor, subtract the divisor, or do neither. The correct (uniquely determined) choice from these three is the one that leaves the remainder after the operation smaller in modulus than (or equal to) half the divisor. Before the next step, the remainder is doubled by shifting it up one binary place; this allows it to take values smaller in modulus than (or equal to) the whole divisor. In the next step, adding or subtracting the divisor can always be arranged to bring this back within the half-divisor range; this can most simply be shown algebraically B B - - < Rn < - 2 2 - B < 2Rn < B B for - B < 2Rn < - -, Rn+1 = 2Rn + B 2 B so that 0 < Rn+l < - 2 B B for - - < 2Rn < - , Rn+1 = 2Rn 2 2 B B so that - - < Rn+1 < - 2 2 B for - < 2Rn < B , Rn+1 = 2Rn - B 2 B so that - - < Rn+1 < 0 2 Thus in all cases it can be arranged that B B - - < Rn+1 < - 2 2 To build up the quotient, one is added to it whenever the divisor is subtracted from the remainder, one is subtracted whenever the divisor is added and if the remainder is left alone, so is the quotient. After each step, the quotient as well as the remainder is shifted up one binary place. An example of this type of division will be given shortly, but first it must be pointed out that the threefold choice at each stage can be replaced with a twofold choice at the cost of a little accuracy. The choice is between adding and subtracting the divisor; the third alter- NS-y-37/11-57

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native, doing neither, is no longer allowed. Here, the remainder after each step is less in modulus than (or equal to) the divisor, and becomes after shift less in modulus than (or equal to) twice the divisor. The range of Remainder values is thus twice as big as in the previous method. It will again be checked that the Remainder stays within range. -B < Rn < B -2B < 2Rn < 2B for -2B < 2Rn < 0, Rn+1 = 2Rn + B so that -B < Rn+l, < B for 0 < 2Rn < 2B, Rn+1 = 2Rn - B so that -B < Rn+l < B Thus in all cases it can be arranged that -B < Rn+1 < B The quotient is built up just as before except that the centre alternative of leaving the quotient alone will now not occur. As far as operations on the remainder are concerned, this last system is exactly the one used in the DEUCE (with slight complications to allow for dividend and divisor of either sign) but the method of building up the quotient is not quite as described. As an example of the two systems described above, we will consider the division of 3 by 7 to five binary places. By this, we mean a process which will produce numbers Q and R such that 3 x 25 = 7 x Q + R, where R lies within certain defined limits. The successive remainders and quotients will be expressed both in binary and decimal notation. In the "Operation" column is marked whether the results in that line have been produced by adding the divisor to the remainder and subtracting one from the quotient (-), by the reverse (+), by neither (o) or by shifting the quotient and remainder (s). (The allocation of the signs "+" and "-" is a little arbitrary; the reader is advised to make quite sure at this stage that he knows which is being called which). The binary numbers are written with their most significant digit on the left. THREE-CHOICE SYSTEM OPERATION REMAINDER QUOTIENT Bin Dec Bin Dec Initially 0 0 0 1 1 3 0 0 o 0 0 0 1 1 3 0 0 s 0 0 1 1 0 6 0 0 NS-y-37/11-57

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THREE-CHOICE SYSTEM (Cont) OPERATION REMAINDER QUOTIENT Bin Dec Bin Dec + 1 1 1 1 1 -1 1 1 s 1 1 1 1 0 -2 1 0 2 o 1 1 1 1 0 -2 1 0 2 s 1 1 1 0 0 -4 1 0 0 4 - 0 0 0 1 1 3 1 1 3 s 0 0 1 1 0 6 1 1 0 6 + 1 1 1 1 1 -1 1 1 1 7 s 1 1 1 1 0 -2 1 1 1 0 14 o 1 1 1 1 0 -2 1 1 1 0 14 Giving the results Q = 14, R= -2, confirmed by the relation 25 x 3 = 7 x 14 - 2. TWO-CHOICE SYSTEM OPERATION REMAINDER QUOTIENT Bin Dec Bin Dec Initially 0 0 0 1 1 3 0 0 + 1 1 1 0 0 -4 1 1 s 1 1 0 0 0 -8 1 0 2 - 1 1 1 1 1 -1 1 1 s 1 1 1 1 0 -2 1 0 2 - 0 0 1 0 1 5 1 1 s 0 1 0 1 0 10 1 0 2 + 0 0 0 1 1 3 1 1 3 s 0 0 1 1 0 6 1 1 0 6 + 1 1 1 1 1 -1 1 1 1 7 s 1 1 1 1 0 -2 1 1 1 0 14 - 0 0 1 0 1 5 1 1 0 1 13 NS-y-37/11-57

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Giving Q = 13, R = 5, confirmed by 25 x 3 = 7 x 13 + 5. The Three-Choice System gives a more accurate quotient; in the example, "14" is closer than "13" to the "true quotient" 25 x 3/7 = 96/7 = 13.7. This is exactly equivalent to the fact that the range of remainder permitted is smaller in the Three-Choice System. In the Two-Choice System, the top digit of the shifted remainder has been underlined. The value of this digit may be used to control the choice of operation for the next step. If this "sign digit" is "0", the shifted remainder is positive and a "+" operation is required next in which the divisor is subtracted from the shifted remainder and one is added to the quotient; if the sign digit is "1", a "-" operation is wanted. An interesting refinement is possible here which has been used in the DEUCE to increase by one the number of binary digits that can be handled. The top digit of the shifted remainder also appears in the remainder before shift (of course); more remarkable still, it is situated one binary place further down in the latter than in the former. The trick is to examine the top digit of the remainder before shift; since in the example the top two digits of the unshifted remainder were always the same, this examination would not be impeded by slicing off the top digit of the remainder all the way down, leaving four-digit working instead of five. It appears at first sight that this will cause the shifted remainder to grow out of range; the number "10" (decimal) which appears in this column will now be represented by "1010" (binary) which would also have to represent "-6" if this were to occur. This does not matter, however; it has already been registered (from the top digit of the unshifted remainder) that the number was positive and that a "+" operation will be called for at the next stage; when this "+" operation has been performed and the divisor (7) subtracted to give the next unshifted remainder (3) the number will be back in range, giving a true sign digit for the next stage. The result is that the divisor can be allowed 31 binary digits, even though this may cause the shifted remainder to have 32 digits sometimes and squeeze its sign digit off the end of the register. An illustration of this by a decimal example would probably not be unwelcome. Suppose we have a decimal desk adding machine with two decimal places in which any carry from the upper digit is simply lost. It is required to double the number 68 by adding it to itself and then subtract- ing 83; the first operation should give 136, but the "1" is lost and only "36" appears. Disaster! But all is not lost; the operation of subtract- ing 83 from 36 should give -100 + 53; again, the "-1" in the hundreds position is lost and only "53" is left in the register. What is more, 2 x 68 - 83 = 53, so that after all our adventures we finish with the right answer. The point is that when a sequence of additions and sub- tractions is performed, provided it is known that the final answer lies within the range of the register, this correct answer will be obtained. NS-y-37/11-57

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It does not matter that intermediate results may go beyond the range of the register. In the case of the divider, it is known that the unshifted remainder obtained at each stage is less in modulus than (or equal to) the divisor, which in turn is within range. It is irrelevant that the intermediate result consisting of the shifted-up remainder may not be within range. There is one snag to this. In the example, shifting the remainder and adding (or subtracting) the divisor were shown as separate steps; this was misleading. In practice, the shift and the addition (or sub- traction) are done simultaneously, so that only the shifted remainder appears, not the unshifted version. The true sign of the remainder is registered in the circuits which control the next stage of the division, but may never be available for inspection as a "sign digit". The opera- tion is not affected, but the "remainder" left at the end of division is the shifted version, not the true value. In the example, this would be 01010, the shifted binary version of "5"; if we have only four-digit working, we are left with "1010", which may equally well be meant for 10 = 2 x 5 and -6 = 2 x (-3). It is impossible to identify the remainder. In many cases this does not matter since only the quotient is of interest. Where it is essential to have the remainder preserved, the only course is to give up the extra digit obtained by this procedure and restrict the divisor to 30 binary figures or less. Even the shifted remainder cannot now reach 32 binary places and must therefore be in range. The quotient is not produced in quite the simple manner so far assumed; or, rather, the logical organisation has been simplified at the cost of making the arithmetic more difficult to understand. In the Two-Choice system described above, the quotient is constructed by adding one in digit positions corresponding to subtractions of the divisor from the remainder and subtracting one in digit positions corres- ponding to additions of the divisor to the remainder. The logical simplification, rather startling at first sight, is to omit all the sub- tractions of one from the quotient; the additions of one and the shifts are performed as before, but the subtractions are simply left out. In the example of dividing 3 by 7 to five binary places, the succes- sive steps are characterised by the symbols, +, - -, +, +, - to build up the quotient, one was added in the top, fourth and fifth binary places, and one was subtracted in the second, third and bottom places. In binary notation, we have:- + 1 0 0 1 1 0 - 1 1 0 0 1 result 0 0 1 1 0 1 NS-y-37/11-57

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The new system leaves out the three subtractions of one, performs only the three additions on one and gives as "quotient" the top row of the above sum, which is 1 0 0 1 1 0. This seems to bear no recognisable relation whatever to the true quotient, 0 0 1 1 0 1. Actually, there is a very close relationship between the two results which is disguised by the small number of digits in this example. Let us consider what we must do to the answer produced by the machine in order to get the true quotient. We will call the machine quotient "M" and the true quotient "Q". From the example, it is clear that if we interchange the ones and zeros in M and subtract the result from the original M, we shall get Q. In other words, wherever the original M has a zero digit, a one must be subtracted; wherever there is a sequence of zeros, a sequence of ones must be subtracted. Take an example; suppose M contains the sequence of digits:- --------- 1 1 0 0 0 0 1 ------- we must subtract--------- 1 1 1 1 ------- to give --------- 1 0 0 0 0 1 1 ------- The sequence of four zeros has in effect been shifted up one binary place, erasing the "1" immediately above it and inserting a "1" in place of the bottom zero of the groups. This will happen to every sequence of zeros in the number. The whole operation may be described as follows:- "remove the "1" from the top of the number (M), shift the whole number up by one place, and insert a "1" in the bottom digit position". Algebraically, we have Q = M - (~M) = M - (2q - M - 1) = 2 M - 2q + 1 where 2q represents the "1" to be removed from the top of M. The exact value of q is a little nebulous; in the example, the division was to five binary places, implying five shifts of the remainder; a "+" step was taken before the first shift and this inserted a "1" in M which was then shifted up five times to give 25. The negated M to be subtracted from M to give Q has ones only opposite the zeros within M, not opposite any zeros there may be above the top digit; if we add this negated M to the original M, we get a sequence of ones up to and including the original top digit of M. This represents 26 - 1. Thus M + (~M) = 26 - 1 (~M) = 26 - M - 1 and Q = M - (~M) = 2M - 26 + 1 NS-y-37/11-57

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In general, for division to p binary places, the digit to be removed from M after shift is 2p+1 The example now becomes clear Take M 1 0 0 1 1 0 Shift up 1 0 0 1 1 0 0 remove the top "1" 0 0 0 1 1 0 0 add it at the bottom 0 0 0 1 1 0 1 giving the true Q However, for some purposes, the M produced is more valuable than would be the true Q. We have Q = 2 M - 2P+1 + 1 from which M = ½(Q - 1) + 2p Approximately, M represents the quotient to one less binary place than Q would have done. This does not matter, since the most convenient arrangement of the Divider gives in all 32 shifts of the quotient and would produce 32 binary places in Q and leave no room for a sign digit. M, with its 32 places only, is from this point of view more convenient. Furthermore, the fact that division is to 32 b.p. (though only 31 bp are produced in M) means that the spurious top digit, 2p, is in fact 232 and is off the top of our 32-digit register. The only remaining distinction between Q and M is the "1" at the bottom. Since the remainder is less than the divisor in absolute value, Q may err by ±1 from a notional absolute value. Calling the notional absolute values Qx and Mx respec- tively, we have:- Qx - 1 < Q < Qx + 1 ½ (Qx - 2) < M < ½ (Qx) Mx - 1 < M < Mx Thus M can never exceed its absolute value and may fall up to one unit below it. If the Machine is being used for pure arithmetic, where numbers may divide exactly, this is very useful since it means that the exact quotient will in fact be found. This is not necessarily true in the case of Q. For comparison, the process of dividing 3 by 7 to five binary places will be set out again, this time with the numbers actually appearing during the automatic process. Remember that the "-" operation now involves no NS-y-37/11-57

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subtraction of one from the quotient. The top remainder digit, shown in brackets, could have been omitted without affecting the operation, provided the exact remainder is not required. The process will be carried out to six binary places, since this will still give only five b.p. in M. OPERATION REMAINDER QUOTIENT Bin Dec Bin Dec Initially (0) 0 0 1 1 3 0 0 + [(1) 1 1 0 0] -4 [1 1 = 20+ 0] s (1) 1 0 0 0 -8 1 0 2 = 21 + 0 - [(1) 1 1 1 1] -1 [1 0 2 = 21 + 0] s (1) 1 1 1 0 -2 1 0 0 4 = 22 + 0 - [(0) 0 1 0 1] 5 [1 0 0 4 = 22 + 0] s (0) 1 0 1 0 10 1 0 0 0 8 = 23 + 0 + [(0) 0 0 1 1] 3 [1 0 0 1 9 = 23 + 1] s (0) 0 1 1 0 6 1 0 0 1 0 18 = 24 + 2 + [(1) 1 1 1 1] -1 [1 0 0 1 1 19 = 24 + 3] s (1) 1 1 1 0 -2 1 0 0 1 1 0 38 = 25 + 6 - [(0) 0 1 0 1] 5 [1 0 0 1 1 0 38 = 25 + 6] s (0) 1 0 1 0 10 1 0 0 1 1 0 0 76 = 26 + 12 + [(0) 0 0 1 1] 3 1 0 0 1 1 0 1 77 = 26 + 13 s (0) 0 1 1 0 6 The square brackets indicate those numbers which are never really visible; the shifts and arithmetic operations take place simultaneously, so that the unshifted results do not appear. The one exception to this is in the final quotient; the shifting element is whipped out of circuit just before the final "1" is added (or not added, in the case of a "-" opera- tion). The unshifted value of the quotient is thus obtained, which is what we really want. Now what about this value of 77 for the quotient? First we must remove the spurious top digit, 26 = 64 (this is done automatically in practice by the process of eventually pushing this digit up into P33 which is, of course, non-existent). This leaves 13, the same quotient as we obtained before. However, the situation with regard to the remainder is less satisfactory. We want the remainder corresponding to the quotient we have in the sense that 2p x A = QB + R NS-y-37/11-57

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In this sense, the remainder is always one jump ahead of the quotient (this is due to the fact that the machine quotient always omits the bottom digit of the proper quotient). To get the remainder, we therefore have to go back one step, with the appropriate shifts. The process is:- Take the remainder produced 6 Remove the last shift 3 Add the divisor 10 Remove the previous shift 5 This is the true remainder in the sense that 25 x 3 = 7 x 13 + 5 No automatic provision is made in the Divider for this remainder recovery. If wanted, it must be programmed separately. Had the top digit of the remainder (in brackets throughout) been omitted, the "10" (decimal) occurring in this process might equally well have stood for "-6", and the true remainder could not have been recovered. The example makes it appear that the remainder recovery process is equiva- lent to taking the entry three above the bottom one in the "remainder" column of the displayed work. This is true only if the last operation performed is a "+". Suppose for example, we had wanted only four binary places. Moving two steps up from the bottom, we see that we would have obtained Q = 38 (6 after removal of the spurious top digit) and R = 10. The remainder recovery process would then be:- Take the "remainder" produced 10 remove the last shift 5 add the divisor 12 remove the previous shift 6 The remainder is 6 in the sense that 24 x 3 = 7 x 6 + 6; the entry in the "remainder" column three above the bottom one is in this case "-1". The point is that the Q produced by the Two-Choice system is always odd; i.e. its bottom digit is always "1". The machine quotient is always this number with the bottom "1" omitted, not necessarily this number with the final step in its calculation omitted, since this final step might have been either the addition or the subtraction of "1". The DEUCE divider will accept divisor and dividend of either sign and produce an appropriately signed quotient. Once it is appreciated that the NS-y-37/11-57

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provisions so far described are sufficient to perform unsigned division, the additions needed to allow for sign are remarkably simple and easy to understand. The only change in the criterion which determines whether the next step is to be a "+" or a "-" operation. In the tables above, this could be stated "if the remainder is negative, do a - operation, otherwise a + operation". To allow for sign, this becomes 'if the remainder and divisor are of opposite sign, do a - operation, otherwise a + operation". Let us see how this new scheme works for dividend and divisor of various signs. For both divisor and dividend positive, the new scheme is just like the old. The other three cases will be described by comparing them in detail with this first case, in which the dividend and divisor will be called "A" and "B" respectively. The second case, that of dividing A by -B, will be illustrated by setting out the division of 3 by -7 to five binary places; this may be compared with the last example. In the present case, a "+" operation consists of subtracting -B from the remainder and adding one to the quotient; a "-" operation consists of adding -B to the remainder. OPERATION REMAINDER QUOTIENT Quotient in Bin Dec Bin Dec division of 3 by +7 Initially 0011 3 0 0 0 - 1100 -4 0 0 1 s 1000 -8 00 0 10 + 1111 -1 01 1 10 s 1110 -2 010 2 100 + 0101 5 011 3 100 s 1010 10 0110 6 1000 - 0011 3 0110 6 1001 s 0110 6 01100 12 10010 - 1111 -1 01100 12 10011 s 1110 -2 011000 24 100110 + 0101 5 011001 25 100110 s 1010 10 0110010 50 1001100 - 0011 3 0110010 50 1001101 s 0110 6 It will be seen that the successive remainders all the way down the list are identical with those in the division of 3 by 7. This may seem NS-y-37/11-57

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fairly obvious, since what one does at each step in both cases is to add 7 if the remainder is negative and subtract 7 if it is positive. The quotient column from the previous example is appended for reference; it will be seen that the unshifted quotient in the present case is always the negated version of this (the shifted quotients, of course, both have zero in the bottom place and are therefore not exact negations of each other). This again is obvious when it is remembered that it now needs a "-" operation to produce the answer in the remainder column previously pro- duced by a "+" operation, and vice versa, and that the successive digits of the quotient may be regarded as a shorthand note of the operations in the order in which they occurred, with a "0" for a "-" operation and a "1" for a "+" operation. The quotient requires a little interpretation. It will be remembered that by the end of the division process the first quotient digit, pro- duced has been shifted up to P33 position; in other words, the first digit has vanished off the top of the register. In the present case, this digit is a zero, in the previous example, a one. Removing the top "1" from the previous quotient, 1001101, left 001101, or 13. Removing the top digit from the present answer leaves 110010, which is interpreted as "-14". In general, if the division of A by B gives a quotient Q, the division of A by (-B) gives as quotient, not (-Q), but (~Q) = -Q - 1; unless an exact quotient is possible, the quotient produced is always algebraically less than the true quotient and as close to it as possible. If an exact quotient is possible, the negative division process will give an answer one less (algebraically) than it should be, but this does not matter much as exact quotients are not usually wanted in signed arith- metic. The remainder has again been taken one step further than the quotient; to get the true remainder, we again take the final R, halve it, add the divisor (in this case negative) and halve again. Take the final R 0110 6 halve it 0011 3 add the divisor (-7) 1001 ____ 1100 -4 halve again 1110 -2 and this is proved by the relation 25 x 3 = (-7) x (-14) -2 The other two cases, the division of -A by B and of -A by -B, are again identical in "shape" with appropriate interchanges of "+" and "-" operations and of zeros and ones in the quotient. Compared with the first two cases, there is also a change of sign throughout the remainder column. In the division of -3 by 7 or of -3 by -7 the first few entries NS-y-37/11-57

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in the remainder column will be -3, 4, 8, 1, 2, -5, -10, -3, etc.; exactly the same entries as in the previous cases, but with all the signs changed. The additions and subtractions of B (=7) have thus also been interchanged; the division of -3 by 7 therefore gives a quotient which is a negated version of that produced in the case where 3 is divided by 7. In the division of -3 by -7 (compared with the 3 by 7 case) the entries in the remainder column are again changed in sign. Here, however, there is also a change of notation caused by the changed sign of the divisor; as in the division of 3 by -7, the subtraction of 7 is a "-" operation represented by a zero in the quotient and the addition of 7 is a "+" operation repre- sented by a one in the quotient; there are thus two negations, which cancel out as far as the quotient is concerned and give exactly the same quotient for the division of -3 by -7 as for the division of 3 by 7. The remainders in the two cases are of opposite sign, however, as would be expected from the fact that if 231A = QB +R then 231(-A) = Q(-B) + (-R) There is one set of circumstances in which dividing (-A) by (-B) does not produce quite the same result as dividing A by B. This is where the remainder becomes zero at some stage in the calculation; since plus zero and minus zero are identical, from this stage on the remainders in the two cases are of the same sign instead of being of opposite sign as they were before. The digits of the two quotients from this stage on are therefore negations of each other. The remainder will only ever become zero in cases where an exact quotient is possible; it has already been said that these cases will lead to an error of one in the quotient if the divisor is negative. The point will be illustrated by the division of 3 by 4 and of -3 by -4 to four binary places. DIVIDE 3 BY 4 DIVIDE -3 BY -4 Op R Q Op R Q Bin Dec Bin Dec Bin Dec Bin Dec Init 0011 3 - - Init 1101 -3 - - + 1111 -1 1 1 + 0001 1 1 1 s 1110 -2 10 2 s 0010 2 10 2 - 0010 2 10 2 - 1110 -2 10 2 s 0100 4 100 4 s 1100 -4 100 4 + 0000 0 101 5 + 0000 0 101 5 s 0000 0 1010 10 s 0000 0 1010 10 + 1100 -4 1011 11 - 1100 -4 1010 10 s 1000 -8 10110 22 s 1000 -8 10100 20 - 1100 -4 10110 22 + 1100 -4 10101 21 NS-y-37/11-57

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DIVIDE 3 BY 4 DIVIDE -3 BY -4 Op R Q Op R Q Bin Dec Bin Dec Bin Dec Bin Dec s 1000 -8 101100 44 s 1000 -8 101010 42 - 1100 -4 101100 44 + 1100 -4 101011 43 s 1000 -8 s 10000 -8 Comparing the two quotients 1 0 1 1 0 0 1 0 1 0 1 1 we see that they are identical up to the point where the remainder becomes zero and after that negations of each other. The entries in the remainder column, on the other hand, are of opposite sign up to the crucial point and after that identical. After removing the spurious top digit, the respective quotients are 1100 = 12 and 1011 = 11. The recovered remainders are ½ [½ (-8) + 4) = 0 and (½ [½ (-8) + (-4)] = -4. These are confirmed by the relationships 24 x 3 = 4 x 12 + 0 and 24 x (-3) = (-4) x 11 + (-4) There is a similar divergence between the results produced respec ively by dividing A by (-B) and by dividing (-A) by B in cases where an exact quotient is possible. The limits on the value of the final R obtained (not the true remainder) are determined by the absolute value of the divisor, not by its sign. The only question is which of two relationships holds: -2B < R < 2B or -2B < R < 2B The answer is that the first holds for all cases. At each stage, the Divider works so as to add something to the remainder if it is negative and to subtract something if it is positive; this "something" is the absolute value of the divisor. In the sign convention used in the DEUCE, zero numbers are counted as positive; a zero remainder will, therefore, always be followed by an unshifted remainder which is negative and equal in absolute value to the divisor. Writing the true (recovered) remainder as r, we always have NS-y-37/11-57

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r = ½(½R + B), whatever the sign of B. Thus for B positive we have -2B < R < 2B - B < ½R < B 0 < ½R+ B < 2B 0 < r < B and for negative B we have 2B < R < -2B B < ½R < -B 2B < ½R + B < 0 B < r < 0 For this value of r, the Q obtained, regarded as a signed number in the normal convention, is always such as to satisfy the relation:- 231 A = QB + r whatever the signs of A and B. OPERATION OF THE DIVIDER To do a division, first send the divisor to TS16 and the dividend to DS213. Then stimulate Trigger DIV by the Instruction "1-24" obeyed in an odd minor cycle. Trigger DIV automatically clears itself after 65 m.c., but the insertion of the final (least significant) digit into the quotient takes place in the minor cycle after DIV is cleared. The whole process, from the time of stimulating Trigger DIV, thus takes 66 minor cycles. At the end of this time, the quotient and modified remainder have been formed in DS212 and DS213 respectively, the dividend has been lost and the divi- sor remains in TS16. The process of division takes place in 33 steps which may be called unit operations. Each unit operation occupies two minor cycles, an odd followed by an even. The unit operation may take either of two forms; in a "+" operation, the contents of TS16 are subtracted from DS21 in the odd minor cycle and one is added to DS21 in the following even minor cycle, both results being afterwards shifted up by one binary place. In a "-" operation, the contents of TS16 are added into DS21 in the odd minor cycle and the addition of one in the even minor cycle is omitted; again, both minor cycles are shifted up. There is one exception to this; the shift is omitted in the 66th minor cycle, that is, in the second (even) half of the 33rd unit operation. Whether a "+" or a "-" operation is to take place is determined by NS-y-37/11-57

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the sign of the number in DS213 at the end of the previous odd minor cycle, taken in conjunction with the sign of the number in TS16. If the signs of these two numbers are the same, a "+" operation takes place, otherwise a "-" operation. The first unit operation takes place in the first two minor cycles of division; whether this is a "+" or a "-" operation depends on the sign of the number initially in DS213, that is the dividend, and the sign of the number in TS16, the divisor. At the end of the first minor cycle, the divisor has been added or subtracted into the dividend to give the first remainder, the remainder after the first step of division. The sign of this first remainder is registered at the end of minor cycle 1, and determines (in conjunction with the sign of the divisor) whether the second unit operation, which happens in minor cycles 3 and 4, will be a "+" or a "-" operation. The sign of the first remainder is, as usual, specified by its top digit, which appears at the end of m.c. 1. As soon as it has been registered, this sign digit is excised, to prevent it spilling over into 212, which is the space reserved for the quotient; this is necessary because the remainder is shifted up, digit by digit, as soon as it has been formed. Thus the sign has to be "remembered" over m.c.2, during which the second half of the first unit operation is happen- ing. and then this remembered sign is used to decide the type of operation required in m.c.3 and 4. This requirement is slightly less stringent than it appears in that the action required in an even minor cycle is only the insertion (or not) of one digit at the bottom of the quotient, and thus occupies only the first microsec of the even minor cycle. Figure 10.10 sets out these requirements; the small circles show the moments at which the remainder sign digit must be registered; the dotted lines represent the periods over which the sign digits must be remembered; the full lines the pair of minor cycles in which occurs the operation they control. The vertical arrows indicate the point at which action is required in the even m.c.; after this point, the value of the sign digit can be forgotten. Figure 10.11 shows the various triggers which control the action; in the figure, accuracy is sacrificed to simplicity. The attentive reader will notice some inconsistencies in timing which will be resolved in due course. Trigger Z is operated at every P1 even and remains static between these times; in view of the 1 microsec delay caused by all wideners and associated delay networks, the state is thus determined by sign digits of numbers occurring in the odd minor cycle. Which way it goes is decided by combining the contents of TS16 with the output of the adder-subtractor unit; in the odd minor cycle, this unit has been used to add or subtract TS16 into DS213 which contained the current remainder, to give the new remainder. Putting all this together, we see that at the end of an odd minor cycle Trigger Z comes on if the sign of the remainder produced in that minor cycle agrees with that of the number in TS16 (the divisor), and goes off if it does not. Trigger Z being on for a pair of minor cycles, (even, odd) means that a "+" operation is wanted in the pair of minor cycles consisting of the same odd minor cycle and the following even NS-y-37/11-57

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minor cycle. All this is a little presumptive; Trigger Z operates all the time, whether or not a division is taking place. The actions des- cribed are wanted only during division, so that Trigger Z must be gated with Trigger DIV before it is allowed to do any work. Trigger DIV is first gated with Trigger ODD to give a signal which marks out the odd minor cycles during division. This signal is in turn gated on to one or other of two lines according to the state of Trigger Z. If Z is put on at the end of a particular odd minor cycle, signal appears, on the line marked "+" for the following odd m.c.; if Z had been put off, the signal would have appeared instead on the line marked "-". Signal on the "-" marks a minor cycle during which TS16 should be added into DS21; no other action is required in a "-" operation. For a "+" operation, TS16 must be subtracted into DS21 during the odd m.c. of "+" signal and P1 must be added into DS21 during the following even m.c.; this is achieved by delaying the "+" signal by about half a minor cycle so that it covers the end of an odd m.c. and the beginning of an even m.c. and using this delayed signal to gate a P1. which must thus be an even P1. Before sketching the complete system, one or two points of detail must be clarified. It will be remembered from the description of the adder-subtractor unit that the signal from HWL enters the unit through the same gate for either addition or subtraction; if subtraction is required, a signal is supplied which negates the HWL signal before it enters the adding circuits and forces a P1 out of the carry apparatus. The two control signals are respectively "add or subtract" and "subtract rather than add", not just "add" and "subtract". The Connections in Figure 10.11 must, therefore, be rearranged as shown in Figure 10.12. At the time when the P1 (even) is to be inserted into the quotient as part of a "+" operation, the digit already in DS21 is always zero. This is because the previous quotient has been shifted up as it was formed, leaving a blank at the bottom, and the sign digit of the remainder, which might have spilled over into this blank, has been pecked out. It is, therefore, immaterial at which of the two inputs to the adder-subtractor unit the P1 (even) is inserted. It happens to be more convenient to insert it at the input which carries the circulation path of DS21, rather than the one where HWL is inserted for addition or subtraction. It has been said that Trigger DIV automatically clears itself after 65 m.c. If, however, a "+" operation has been called for m.c. 65 and 66, the insertion of P1 (even) into the quotient in m.c. 66 still takes place. This is because, although the "DIV & ODD' signal has its last fling in m.c. 65 and is not seen again, its spirit lingers on through the 15 micro- sec delay element to gate a P1 during m.c.66. The fact that Trigger DIV is off at this time means that the final quotient is not shifted during formation as all its predecessors have been. A complete, though still rather inaccurate, schematic of the Divider is given in Figure 10.13. After all that has been said, it should need NS-y-37/11-57

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no further explanation. Division is always clone with TCB on, since the quotient and remainder are always two separate numbers in the two halves of DS21. A connection is made from Trigger DIV through a beginning element to stimulate TCB. This ensures that the addition of one required at the beginning of a subtraction in an odd m.c. is always available, saving a connection similar to that from D23 Destination gate which imitates TCB. It also means that gates which require a Q1 input can be connected instead to M1, where this is convenient for electronic reasons. The Q32 inhibiting gate just before the shifting delay has a dual function. It nips off the sign digit of each successive remainder as it is formed, preventing spill-over into the quotient and also, at the end of m.c. 64, removes the spurious top digit generated in the method of divi- sion used, preventing spill into the remainder. There are certain limits on the sizes of A and B for a correct quo- tient to be obtained; these are that A, B and the quotient 231 A/B must all be single-length in the signed convention. The last condition implies that in absolute value A must not exceed B, and can equal B only if A is negative and B is positive. COMPLETE MILTIPLIER-DIVIDER UNIT Figure 10.14 gives the complete layout of the unit. All the signals in the adder-subtractor section are 1 microsec later, owing to the wideners and compensating delays at all the inputs. Some input signals are at HWE timing (which is the same as clock-pulse timing) and some are at HWL timing which is one-sixth of a microsec later. Small delays are inserted where necessary to bring all signals in the adder-subtractor section to HWL timing, or rather to the corresponding wide-pulse timing which is such as exactly to straddle the narrow HWL pulses. This timing is illustrated in Figure 10.15. The reader will find it an interesting excercise to work out the reason for all the small delays shown in the diagram, and to dis- cover which of them, if any, have been given the wrong value. The diagram will repay a good deal of study; in considering the division operation, it will be remembered that TCB is on during division, so that lines marked "M1" in fact carry every Q1. THE COUNTER The only part remaining to be described in detail is the "Counter" which switches off Trigger MULT or DIV (whichever is on) after 65 m.c. Figure 10.16 shows the arrangements in more detail than the main diagram. It will be remembered that although MULT and DIV officially come on at the beginning on an odd minor cycle, they are actually stimulated at about P28 time in the preceding even m.c. Shortly after either has been put on, Trigger L in turn is stimulated. Trigger L has two functions; it pre- vents signal from the Pt (even) connection from clearing MULT (or DIV, NS-y-37/11-57

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as the case may be), and also permits the five counting triggers to operate. The counting circuits are arranged to give out a short pulse coincident with the 32nd P1 (odd) pulse received; this clears Trigger L and allows the next P1 (even) to clear DIV (or MULT). Numbering the minor cycles of Multiplication (or Division) from 1 to 65, we see that the first P1 (odd) pulse attacks the counter in m.c.3, since the delay in the connection from Trigger L prevents the P1 in m.c.1 from getting through. The 32nd P1 (odd) pulse, therefore, comes in m.c. 65; Trigger L is cleared at P1 time in m.c. 65 and lets through the P1 in m.c.66 to clear DIV (or MULT). A little more detail on the Counter might be in order. It consists of five changeover triggers in series, each changing over at any time when the previous one goes from off to on. When the fifth goes from off to on, a signal is sent to clear Trigger L. The output from Trigger L is connec- ted to all five counting triggers in such a way that if Trigger L is off all the five triggers are held off and cannot be stimulated. We may, therefore, assume that the normal state of affairs between operations of division or multiplication is for all five triggers to be off. Represent- ing a trigger which is off and on respectively by the symbols "0" and "1" we can set out the sequence of events as below. The successive states come into being at P1 times in successive odd minor cycles, as shown: At P1 IN M.C. 5 TRIGGERS TAKE UP POSITION 1st 2nd 3rd 4th 5th Initially 0 0 0 0 0 3 1 0 0 0 0 5 0 1 0 0 0 7 1 1 0 0 0 9 0 0 1 0 0 (2n+1) binary configuration representing "n" 61 0 1 1 1 1 63 1 1 1 1 1 65 0 0 0 0 0- to clear L. NS-y-37/11-57

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THE MAGNETIC STORE

The magnetic store consists of a rotating drum the surface of which is capable of being magnetised by electric current passed through a station- ary "writing head" held very close to the surface of the drum. The nature of this head need not concern us at the moment. The magnetisation on the drum remains there indefinitely until modified by a further signal applied to the head. The head is extremely small, and induces only a very narrow band of magnetic signal; thus with a single head in a fixed position it is possible to write one narrow track of information round the circum- ference of the drum. This information consists of a series of very small magnetic dipoles, magnetisation in one direction representing a digit "0" and in the other direction a digit "1". 1024 such dipoles are inscribed on a circumferential track, so that each track carries the same amount of information as one DL. More than one track may be written either by moving a single head up and down the drum or by having a number of heads. In the DEUCE, these techniques are combined. There are 16 writing heads mounted rigidly together in a block; this block is capable of being moved into any of 16 positions along the drum. Any one of 256 tracks may be written by first shifting the whole block to the right station and then sending the writing signal to the appropriate head. In all, the drum can carry 8192 words, the contents of 256 DL's, with about the same amount of electronic equipment that would be needed for eight DL's. The stored information is read from the drum by one of a block of 16 reading heads. This block may also be shifted into any of 16 positions to cover the 256 tracks. The movements of the writing head block and the reading head block are independent. The two blocks are identical, includ- ing the heads themselves, though the electronic connections to a reading head and a writing head are not the same. ARRANGEMENT OF TRACKS ON THE DRUM The 16 tracks covered by a given head are adjacent ones on the drum; the overall range of movement of either block is thus one sixteenth of its length (or rather 15/255 of the distance between the extreme top and bottom tracks). The distance apart of adjacent heads on the block is sixteen times the separation between adjacent tracks on the drum. The numbering by which the tracks are identified, however, would seem to deny this arrangement. The tracks are numbered from 0 to 255; each successive block of sixteen numbers refers to the sixteen tracks which can be reached with the head block stationary in one of its sixteen positions. An example may clarify this. Suppose it is required to write information successively on each of the 256 tracks in turn, the operation is as follows. Put writing head block in position "0", write on track 0 through NS-y-37/11-57

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head 0, write on track 1 through head 1 and so on till we have written on track 15 through head 15, next shift write heads to position 1, write on track 16 through head 0, write on track 17 through head 1, and so on, write on track 31 through head 15, shift write heads to position 2, write on track 32 through head 0, track 33 through head 1, track 47 through head 15; eventually, the write heads are shifted to position 15, track 240 is reached through head 0, track 241 through head 1 and track 255 through head 15. It will be seen that the order of tracks on the drum according to their number is 0, 16. 32 ... 224, 240, 1, 17, 33 ... 225, 241, 2, 18, 34 ... 226, 242, etc. Strangely enough, this same arrange- ment of the numbers 0 to 255 also represents the distance along the drum from track 0 at which the successively numbered tracks in the convention just defined will be found. In other words, track 1 is in position 16, track 2 in position 32, track 15 in position 240, track 16 in position 1, etc., where "in position 32", for instance, means "the 32nd track counting along the drum". This complicated and not very useful piece of informa- tion is given in order to prepare the reader for the even more complicated and quite essential information which is to follow. ARRANGEMENT OF DIGITS ON A TRACK It would be most natural to have the drum make one revolution in a Major Cycle; the successive digits from a DL could then be written on a track as they emerged from the delay, in the order in which they were stored. The reading process would be equally simple. Unfortunately, this requires an angular velocity of 60,000 r.p.m., which was not considered practical. What then is the alternative? Would a shunting storage posi- tion be needed to exchange digits at full speed with a DL and at some slower speed with the drum? The solution of this problem is simple in conception, but becomes less simple when its implications are considered in detail. The drum makes one revolution in exactly nine Major Cycles, or about 6,500 r.p.m. The requirement is to write the 1024 digits stored in a DL at 1024 equally spaced positions round a track. This must take at least nine Major Cycles, the period required for the complete track to pass by a writing head. During this time, the complete information in the DL emerges from the delay nine times in succession. The method is to pick out every ninth digit emerging from the delay, ignoring the eight inter- vening ones, and to record only these ninth digits on the drum. In this way, each ninth part of the drum circumference carries a sample of digits taken at equal intervals along the whole DL. Because of the fact that 9 and 1024 have no common factor, these nine samples contain jointly just one copy of every digit in the DL. Let us look at this in a little more detail. For this purpose, the digits in a DL are regarded as being numbered from D1 to D1024. Suppose D1 has just been recorded on the drum; to fix our ideas, we will say that D1 is recorded in digit position "1" on the NS-y-37/11-57

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track. D2 to D9 are ignored and D10 is recorded next to DI on the track, that is, in position "2". D19 follows, then D28, D37 and D46 in position "6". After nearly a Major Cycle we are nearly one-ninth of the way round the drum and are recording, say D1009 in position 113; the 114th digit recorded is D1018; D1019 to D1024, D1 and D2 are ignored and D3 is recorded in position 115. Then we have D12 in postion 116, D21 in posi- tion 117, and after nearly two Major Cycles, D1011 in position 227, D1020 in position 228 and D5 (=D1029) in position 229. After a further Major Cycle, the 342nd digit recorded is D1022 and the 343rd D7; the 456th is D1024, the 457th D9, the 569th D1017, the 570th D2, the 683rd D1019, the 684th D4, the 595th D1021, the 798th D6, the 911th D1023, the 912th D8 and the 1024th is D1016. The 1025th digit to be recorded would be D1025, which is Dl emerging from the delay for the tenth time; since the drum revolves in exactly nine Major Cycles, the writing head is now over exactly the same point on the track as that on which D1 was written in the previous revolution. If writing is now stopped, the process of recording the digits from the DL once each on the track has been completed in one revolution or nine Major Cycles. Since, however, rewriting the same digit on the same bit of the track has no additional effect, there is no objection to an overlap in which some of the digits are written for a second time. It has been found convenient for electronic reasons to allow such an overlap on the DEUCE magnetic store. READING FROM THE DRUM So much for writing. The 1024 digits have each been put on the track, but what use are they in this garbled order? How can they be returned to a DL, when required, in their correct sequence? The answer to this is quite simple. Each digit appears at the writing head every exact multiple of nine Major Cycles after it was written. If at this moment it is read from the drum and replaced in the DL, it will occupy the same position in the DL as that from which it originally came. Nine microsec later, another digit on the track reaches the writing head and may also be replaced in the DL in its correct position. If this process is repeated once every nine microsec for nine Major Cycles, the total result will be that every digit from the track has been replaced in its correct position in the DL. The circulation path of the DL must be restored immediately after inserting each digit so that digits previously read in will not be lost during subsequent sweeps of the DL. However, this process requires that the reading and writing head blocks should be in identical positions round the circumference of the drum, which is impossible. This difficulty is overcome by making use of the fact that, in our previous convention of writing D1 in position "1" of the track, D2 is written in position "570", about five-ninths of the way round the drum. In Figure 11.1 markers "A" and "B" are shown on the edge of the drum separated by 569/1024 of the circumference. If a DL of information has been placed on a track as described, the digits currently at A and B for any angular position of the drum will always. be adjacent NS-y-37/11-57

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digits from the DL. A writing process at A starting with D1, D10, D19, etc., would have exactly the same final effect as a writing process at B commencing at the same moment and proceeding with D2, D11, D20, etc. More accurately the B process starts one microsec later, so that the B position must be slightly further round the drum from A, in the direction of motion; the exact separation is 569 + 1 of the circumference. 1024 9 x 1024 ARRANGEMENT OF HEAD BLOCKS ROUND THE DRUM We are now more comfortably placed; there are two positions from which the required results may be obtained, of which one may be used for writing and the other for reading. In practice, the reading head block is stationed at A and the writing head block at B. Arrangements are made for a one-digit shift in the connection from the DL to the writing heads. There is, of course, no virtue in starting the reading or writing operation at any particular point on the track; either may begin and end at any time, provided that it proceeds for at least nine Major Cycles. The period is set by a trigger in the Magnetic Store circuits which allows a margin of error of about one Major Cycle over the nine required. A further half Major Cycle at either end is occupied by arrangements for a gradual start and stop to the writing operation, making a total of 11 Major Cycles for the actual reading or writing operation. Two Major Cycles are occupied by the process of head selection, so that about 13 Major Cycles in all are required to carry out a Magnetic Transfer Instruction. MAGNETIC CLOCK PULSES For reading, a waveform is required which will break the circulation path of DL11 for one microsec in every nine to permit the insertion of a digit read from the drum. This waveform, consisting of a 1 microsec signal every 9 microsec is called "Magnetic Clock Pulses" or MCP. The same signal delayed by 1 microsec is used to pick out digits from DL11 to be written on the drum - it will be remembered that writing is at "B" on the drum, where D2 occurs at the moment when D1 is at "A", (more accurate- ly 1 microsec after that moment, which is not much in a revolution time of 9216 microsec). MCP are generated from Clock Pulses by means of a frequency divider circuit; this consists of two frequency-dividing trigger circuits in series, each of which is arranged to give out one pulse for every three it received (Figure 11.2). DRUM SERVOMECHANISM A servomechanism is used to ensure that the drum rotates once in exactly nine Major Cycles. Attached to the drum is a disc with 1024 teeth spaced equally round its circumference. A magnetic reading head generates from these a series of 1024 electric pulses in each revolution; NS-y-37/11-57

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these are called Drum Pulses or DP. The MCP and the DP are fed into a discriminator circuit which compares their phase. The intention is that the drum should revolve so as to keep each DP just midway between two MCP; the discriminator output voltage is zero when this is true, and positive or negative respectively when the DP are early or late. This voltage is fed into the drum driving circuits in such a way as to tend to correct the error; it is, in fact, more than sufficient to correct it. In this way, any deviation from the correct position is at once sternly opposed. However, small errors from true position are bound to occur; it was therefore thought desirable to allow as much margin of error as possible; in other words, to maximise the distance from true which the drum could move before affecting the operation of the Magnetic Store. The DP have been introduced into the signal gating circuits to help with this, as we shall see shortly. SIGNALS ON THE DRUM We will now consider the actual waveforms of the electrical signals applied to a writing head to write digits on a track and of those received from a reading head as a track of information passes by it. These wave- forms are more complex than has yet been admitted. The obvious way would be to apply, say, a solid 9 microsec of posi- tive signal for a "1" and a solid 9 microsec of negative signal for a "0", but there are several objections to this. In the first place, the signal obtained at a reading head is the differential of that originally applied at the corresponding writing head. It is believed that this differentia- tion takes place solely on reading and that the magnetic writing on the drum is an exact copy of the input waveform, with magnetisations in the two opposite directions for the two types of input signal; however, we will not go into this, since we are concerned not in the least with the little magnets on the drum but only with the relation between the electri- cal signals at the two heads. This differentiation means that the simple type of input described above would give a signal at the output only at the end of any string of "1"s and of any string of "0"s. While it would not be impossible to regenerate the input signal from this, the technical problems would be embarrassing. Another point is that sufficient signal must be applied to magnetise the drum surface to saturation; otherwise the magnetisation obtained might depend on the previous state of magnetisation. Such large signals are much more easily handled if a.c. connections can be used, which implies that the mean level of current in the applied signal must be independent of how many "0"s and "l"s it contains. For these and other technical reasons, the form of input signal shown in Figure 11.3 has been adopted; each digit period of 9 microsec is split in two, signals of opposite polarities being applied for the two halves. "0" is represented by 4 microsec negative followed by 4½ microsec NS-y-37/11-57

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positive, "1" by the reverse. This signal has a constant mean level for any arrangement of input digits. Furthermore, its differential gives a distinct indication of each digit; the upward stroke in the centre of a digit period containing a "0" is reflected by a positive pulse in the differentiated signal; the downward stroke in the centre of a "1" causes a negative pulse in the differential. The conjectured magnetisation and the output signal at the reading head are also shown in the figure. Since the differentiated output pulses occur 4½ microsec after the start of the corresponding input periods, the read head block position must be advanced relatively to the writing head block by 1 of the drum circumference. 2048 MAGNETIC INSTRUCTIONS The working of the drum itself and the precise nature of the electri- cal signals required at a writing head and received from a reading head have now been described. There remain the mechanisms by which these signals are respectively generated and made use of. D30 and D31 are used solely for operations concerning the Magnetic Store; D30 for reading or writing, and D31 for shifting heads. An even characteristic indicates reading and shift reading heads respectively and an odd characteristic indicates writing and shift writing heads respectiv- ly. The Source number indicates the head or head position required. For example, to read from track 121 (= 7 x 16 + 9) the two Instructions required are "7-31s" which puts the reading heads in position 7 and "9-30s" which reads the track under reading head 9 into DL11. To write on track 55 (=3 x 16 + 7) we need the two Instructions, "3-311" which shifts the writing heads into position 3 and "7-301" which writes the contents of DL11 on the track under writing head 7. Of course, if it had been known that the reading heads were already in position 7 and the writing heads in position 3, the two transfers to D31 would have been unnecessary. The second digit of the Characteristic is irrelevant in these Instructions, so that "d" and "q" would have done equally well instead of "s" and "l" respectively. These Instructions merely initiate the reading, writing or shifting operations which then proceed to completion under the control of timing circuits within the Magnetic Storage organisation. During this time, the rest of the Computer is free to proceed with any sequence of operation which do not involve DL11 or the Magnetics. The Source number and first Characteristic digit of the initiating Instruction must, therefore, be registered within the Magnetics organisation independently of the changing Source and Characteristic digits on the IS triggers of Control. This requires 13 Magnetic Staticiser triggers; four each for read head position, write head position and head selection and one for the first Characteristic digit. These remain static between Magnetic Instructions and change their state only at the time of a transfer to D30 or D31; even then, only one of the three sets of four staticisers can be changed at a time. NS-y-37/11-57

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MAGNETIC STATICISERS Figure 11.4 shows the staticiser connections by themselves. The three blocks of four staticisers are identical, but are reached by differ- ent routes. The read head position staticisers, for example, are set by a transfer to D31 with characteristic 0 (or 2). The signal from the D31 gate is routed to the Magnetic Staticisers (Read) (MSR) rather than the MSW, because IS15 represents the first digit of the Characteristic in the current Instruction, and gives no signal if the Characteristic is even. The four staticiser triggers MSR5, MSR6, MSR7 and MSR8 are now set according to the values of the 5th, 6th, 7th and 8th digits of the Instruction word, that is the first four digits of the Source number. Similarly, a "long" transfer to D31 sets the four MSW triggers. The four MSR triggers are connected directly to the mechanism which holds the read head block in the correct position. With the four stati- cisers static, the block stands still. As soon as any or all of them are changed by a "single" transfer to D31, the head block starts to move up or down the drum towards the new position indicated by the revised set-up of the four staticisers. Allowing a margin for safety, it will be 35 milli- sec before it arrives there. Each of the 16 possible configurations of the four MSR staticisers jointly may be taken as representing a binary number from 0 to 15. This number represents the distance along the drum, taking the separating between adjacent tracks on the drum as a unit of the position to which the head block will move, or in which it will remain. The mechanism by which this result is achieved will not be des- cribed in the present report, as it is more appropriate to a manual on circuitry than to one on logical operation. The four MSW staticisers control the position of the writing head block in exactly the same way. The third set of staticisers, MSH5, MSH6, MSH7 and MSH8, select which of the 16 heads from the block is to be used for reading or writing. These four staticiser triggers feed a Tree similar in function to the NIS, Source and Destination Trees controlled by the IS staticiser triggers. This Tree has four input lines and 16 output lines numbered 0 to 15; a signal appears on just one of the output lines, selected in accordance with the binary number represented by the configuration of the four MSH staticiser triggers. Each of the 16 outputs is connected to one of the reading heads and one of the writing heads. Thus the PH staticisers decide simultaneously which reading head will be used if we are reading and which writing head will be used if we are writing. The process of head selection takes about 2 millisec compared with 35 millisec for a head shift; this is why separate sets of staticisers are provided for read and write head shifting and only one communal set of staticisers for head selection. OPERATION OF A READ OR WRITE INSTRUCTION The operation of the Instruction "9-30s", which reads from the track under reading head 9 into DL11, has two phases. First the MSH staticisers NS-y-37/11-57

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are set to select head 9; then a reading operation is initiated. The Instruction "7-301" selects head 7 and then initiates a writing operation. Both reading and writing have to continue automatically for the same length of time, about 10 millisec. They are, therefore, controlled by a common trigger called Magnetic Transtim or MTT, which is stimulated (after a delay of 2 millisec) by either a read or a write Instruction. The MTT signal is then gated by the output of the MS15 Staticiser trigger on to one of two lines called Read MTT and Write MTT respectively. The con- nections are shown in Figure 11.5. Subsequent arrangements are made to smooth the Write MTT signal so that it takes half a millisec after the start of MTT to reach its full value and the same time at the end to fall back to zero. To allow for the slow rise, MTT stays on for 10½ millisec in all. Read MTT, therefore, stays on for ½ millisec longer than neces- sary but this does not matter much. The stimulation of MTT by a read or write Instruction is delayed 2 millisec by trigger MD; this is to allow time for the setting up of the head selection tree. The connections from triggers MTT and MD labelled "to CMI" will be explained in the next paragraph. CONTROL-MAGNETICS INTERLOCK While reading, writing or head-shifting are in progress, the DEUCE is free to proceed with any sequence of Instructions which do not use D30, D31, S11 or D11; when one of these is called, the Instruction concerned is held suspended in TS COUNT until the completion of the magnetic operation. To achieve this, a signal called "Control-Magnetics Interlock" or CMI is sent from Magnetics to Control whenever D30, D31, S11 or D11 is called during the process of a magnetic operation. This CMI signal is manufactured by combining in a 2-gate two separate signals, one of which indicates that reading, writing or head-shifting has been called or is taking place, and the other that D30, D31, S11 or D11 has been called. For reading or writing the fact that MD or MTT is on is sufficient indication; the extra connection from MTT through a ½ millisec delay allows time for the slow fall to zero of Write MTT at the end of a writing operation. These arrangements to deal with head-shifting will now be described. A head-shift occurs when any of the MSR or MSW staticiser triggers changes its state. Each of these triggers is fitted with a beginning and an end element; the outputs of all these are connected together to stimulate a trigger called Shift Delay or SD which automatically extinguishes itself after 35 millisec, a sufficient period to cover the head shift with a margin for safety. The complete CMI connections are shown in Figure 11.6 which includes a section of Control as a remainder. By clearing trigger R soon after trigger P comes on, CMI signal prevents the initiation of Transtim for an Instruction, which is taboo. It might seem that any magnetic Instruction would generate CMI signal and thus prevent itself from taking place, but this is not so; CMI signal prevents NS-y-37/11-57

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the initiation of Transtim, but has no effect on an Instruction which has already stimulated trigger P before CMI signal starts, CONNECTIONS WITH DL11 The connections between DL11 and the reading and writing heads are shown in Figure 11.7. The J-K gap is used rather than the G-H gap because J has the associated point N which carries the negated words from DL11. It will be remembered that reading is controlled by the MCP signal which covers 1 microsec in every 9 microsec, and writing by the same signal after I microsec delay. WRITING CONNECTIONS For writing, the MCP(D1) signal is used to select every ninth digit from DL11. If this digit is a "1" a pulse comes from J to stimulate trig- ger WW (Write Wide); if it is a "0" a pulse from N clears WW. Thus the signal from WW represents in 9 microsec pulses the digits from DL11 in the order in which they are to be written on the drum, not in their natural order. These pulses are wide in the sense that the pulse width and pulse separation are equal; a sequence of "1"s is represented by continuous signal, alternate "1"s and "0"s by alternate periods of 9 microsec in which a signal is present and absent. Now we come to the introduction of Drum Pulses, an ingenious device which greatly increases the permissible error in instantaneous drum position. The DP are combined with Write Wide in the Write Wave-Form trigger (WWF); the two inputs and the output of this are shown in Figure 11.8 (a, b and c). Each DP is shown midway between two MCP, which is where it should be; if the drum has an instantaneous positional error in either direction, the DP will be correspondingly early or late. If the discrepancy is less than 4½ microsec either way, the DP will still fall within the same Write Wide digit period, and the Write Wave-Form signal will be unchanged except for a shift forward or backward (Figure 11.8 (d and e) show the DP early and the corresponding Write Wave-Form); furthermore, this shift will be locked to the drum position, so that the digit will be written at the same point on the drum even though this point may pass the writing head a bit earlier or later than it should. The effect is somewhat similar to that of a flexible coupling. The Write Wave-Form is generated all the time, whether or not a write operation is in progress; thus the rearranged digits from DL11 are always ready to be written on the drum as soon as Write MTT signal is applied. The direct connection to a writing head is through a powerful amplifier; any disturbance in the applied signals is therefore liable to interfere with the pattern on the track. These may include sudden start- ing or stopping of Write Wave-Form signal or Write MTT signal or switching of the head selector. Precautions must be taken against these effects. One precaution is that WMTT is connected through an element which smooths NS-y-37/11-57

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off its leading and trailing edges; in other words, the effective WMTT rises slowly from zero to its full value and at the end of the writing operation, falls slowly back to zero. This smoothing element is shown in the figure as a delay because this is the nearest thing to it in our vocabulary of logical symbols. The smoothed WMTT is combined with WWF in a 2-gate, so that the effective WWF also comes and goes not with a bang but with a whimper. The danger of head-switching signals being written on the drum is thus averted by a belt-and-braces technique of connecting the smoothed WMTT signal to the write head amplifiers directly as well as indirectly through its effect on the applied WWF. This direct connection effectively switches off the amplifiers completely, so that there is now no danger whatever of writing anything in the absence of WMTT signal. The gradualisation technique also obviates the technical difficulty of sharply dousing a good amplifier. When a writing operation is called, the MSH tree first switches the head selection signal to the required head. After the 2 millisec delay which allows for the completion of this, WMTT signal is initiated and takes ½ millisec to build up to its full value; this both brings the write head amplifier into operation and applies WWF signal to it. After a further 10 millisec WMTT begins to fade away, dousing the amplifier and the WWF signal. Figure 11.9 shows this timing. READING CONNECTIONS Just one of the reading heads is always selected, so that the Read Wave-form (RWF) from this head is always combined with DP to operate the Read Wide (RW) generator trigger. The waveforms, together with the out- put of the subsequent Clock Pulse gate, are shown in Figure 11.10. The RWF signal is shown inverted compared with that in Figure 11.3; this merely means that the convention here is to equate negative voltage with "signal on". Since the DP and the RWF signal are both locked to the instantaneous drum position, there is no gating difficulty at this stage; if the drum is early or late, the RW signal will slide backwards or for- wards along the stream of Clock Pulses. This means that each digit "1" from the drum is represented by a sequence of 9CP (or perhaps 8, with half a CP at either end) but that the beginning and end of this sequence may vary by a few CP in either direction with variation in the instantan- eous drum position. During a reading operation, one CP from each sequence of 9 is picked out by a MCP for insertion into DL11, the middle one if the drum position is correct. The system will work properly unless the instan- taneous drum position is so far out that the CP level with the correspond- ing MCP is exluded from the sequence of nine, that is unless the drum is early or late by 4½ microsec or more. These sequences of 9 pulses for a "1" and 9 blanks for a "0" are generated all the time in accordance with the successive digits of the track under the selected reading head. Read MTT acts by gating the MCP NS-y-37/11-57

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which inserts members of these sequences into DL11. The action of the MCP in this case is to break the circulation path of DL11 for 1 microsec, losing that digit from DL11 and replacing it with the corresponding digit from the drum. If a reading operation is initiated at a time when DL11 is already full of words, the old digits will be replaced with the new ones during nine sweeps of DL11; at any time during the process the digits in DL11 are a fairly random-looking selection of new digits from the drum and old digits which have yet to be replaced. GENERAL Figure 11.11 is a complete functional diagram of the Magnetics; no further description will be given of it, since it is merely the synthesis of parts that have already been described. One further point must, how- ever, be made. The servo-mechanism provides only that the DP run midway between the MCP; it does not distinguish between particular DP. If the DEUCE is switched off and then switched on again, the drum may lock into any of 1024 positions. A track previously written on the drum may still be read back into DL11 and will comprise the same digits in the same order, but shifted round by an arbitrary number of places. This makes the information pretty well useless, so that the drum cannot be used for storing permanently information such as subroutines which may be wanted in any program. To provide absolute synchronisation of the drum would have required considerable extra complications which were not considered worth while in view of the fact that the whole 256 track drum can be filled from cards read at the input in about four minutes. This could be improved by using only 255 tracks for information and sacrificing one to contain a pattern by which shift in drum position could be identified. In this case, a program could be made which would read each track in turn (starting with the position marking track), shift it round to its true position, and replace it. This would take only about a minute for the whole drum. NS-y-37/11-57

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THE READER AND PUNCH

The DEUCE communicates with the outside world through the medium of standard 80-column Hollerith Punched Cards. Only 32 of the 80 columns are used directly; they are chosen to be columns 21 to 52, since this leaves room for other information to be punched or written on either end of the card. The Reader and Punch are both adapted from standard Hollerith Machines. In both cases, the mechanical card-feeding and card-reading parts of the machine are made from ordinary Hollerith pieces. The control and timing of the feed, the switching of the reading and punching signals and the transfer of control signals to and from the DEUCE are performed by relay circuits built on to the Punch, the Reader and the Control Panel. THE READER Cards to be read are placed in the Hopper of the Reader; they pass through the mechanism and emerge in the Stacker. If the machine is stationary, there are positions for four cards between the first card in the Hopper and the last card in the Stacker. These positions are numbered 2, 3, 4 and 5, the first card position in the Hopper being number 1 and the last card in the Stacker number 6. A unit operation of the Reader (the least it can do), called a "Card Cycle", is the movement forward by one position of every card in the machine. If there were previously a card in position 3, it moves into position 4, and it is during this move- ment that the card is read. In order to be read, a card passes between a metal roller and a row of eighty equally spaced wire brushes. The roller is held at -300 volts. When a row of the card is in position opposite the brushes, only those brushes make contact with the roller which are opposite holes in that row of the card; the other brushes are insulated from the roller by the card. Thus the configuration of holes and blank spaces in the card row is translated into potentials on the brushes, those corresponding to holes being at -300v and the others being floating (at least as far as the Reader connections are concerned). Figure 12.1 shows the six card positions, the roller and the brushes. Only 32 of the 80 brushes are connected to the Input Dynamiciser of the DEUCE. though one other is used for another purpose. The movement of cards is slightly more complicated than has been described; they do not necessarily all move at once. There are two parts, the lower drive which moves cards from positions 4 to 5 and 5 to 6, and the upper drive which moves cards from positions 1 to 2, 2 to 3 and 3 to 4. There are also two NS-y-37/11-57

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clutches, the lower clutch which connects the lower drive to a motor and the upper clutch which connects the upper drive to the lower drive. If the upper clutch is out, the lower clutch in and the motor turning, the lower drive will operate without the upper drive; the upper drive, on the other hand, can never work without the lower drive. The switching of the motor and the two clutches is controlled by the relay circuits built on to the Reader. To start the Reader if it is still, both clutches and the motor are brought on simultaneously and the whole thing starts at once. When it is decided to stop the Reader, the upper clutch drops out at the end of the current card cycle and the upper drive stops. This freezes the cards at the time in positions 1, 2 and 3. The lower clutch remains engaged for another two cycles, so that the cards from positions 4 and 5 are decanted into the stacker; and then disengages. The motor is switched off at some time during these two cycles determined by the setting of a cam. This means that the lower drive slows down a little before the lower clutch breaks, thus reducing the strain on the lower clutch. It is possible, in circumstances that are about to be explained, for cards to pass through the Reader without their contents being made avail- able to the DEUCE on the Input Dynamiciser. There are thus three types of card cycle; a genuine Reading Cycle, a Feeding Cycle, and a cycle in which only the lower drive is operating. This last type of cycle occurs only as a postcript to a sequence of one or more reading or feeding cycles. There are three keys on the Reader called respectively Initial Input, Run Out and Run In; each operates by being pressed downward from its normal horizontal position. The Run In Key also operates when pressed upwards, but this time with a different effect, that of stopping the Reader whatever it is doing. The action of the Reader will be illustrated by a few examples. Suppose first that the DEUCE is doing a program in which it will shortly require to read in certain information from cards. These cards are placed in the Hopper and the Run In Key pressed. The Reader does two Feeding Cycles which bring the front card from the Hopper into position 3. At this point, a relay called Q comes on in the Reader which indicates that there is a card ready to be read (Relay Q also lights an indicating lamp on the Reader). In due course, the program reaches the point where the information is required and obeys the Instruction "12-24" which stimulates Trigger READ. The fact that both Trigger READ and relay Q are on causes Reading Cycles to start, and the cards from the Hopper pass successively from position 3 to 4 past the Reading Brushes. As the first Reading Cycle starts, the Source 0 connections are removed from the row of Input Dynamiciser lamps on the Control Panel and connected instead to 32 of the Reading Brushes. These connections therefore carry the con- figurations on successive rows as they pass the brushes. As each row of NS-y-37/11-57

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each card comes into position under the brushes, a Single-Shot signal is sent from the Reader to Control. For a period covering the time of the twelfth (last) row of each card, TIL signal (Twelfth Impulse Line) is sent to the Destination Triggers circuits for transmission to Trigger D on Control (if required) by the Instruction "2-24". When all the information required has been assimilated, the Instruc- tion "9-24" is obeyed which clears Trigger READ. This may happen in the middle of a card, but from that moment there are no further Single-Shot or TIL signals, and the Source 0 connections revert to the ID lamps on the Control Panel. At the end of the current card cycle, the upper clutch drops out and the upper drive stops; the lower drive continues for a further two cycles. The effect would have been the same if Trigger READ had been stimu- lated first and the cards run in afterwards. Instructions of the form "0-D" which read from a card to any Destination D are always made Stoppers; they are not obeyed until a row of a card comes along, however long the wait. Pressing the Run In Key gives two Feeding Cycles at the end of which relay Q comes on. Since Trigger READ is already on, the first Reading Cycle starts immediately, following right on from the second Feeding Cycle. Relay Q may be cleared at any time by raising the Run In Key and then returning it to normal. Reading Cycles cannot now take place, even if Trigger READ is stimulated, in spite of the fact that a card may be present in position 3. If relay Q is cleared during the process of reading, the current Reading Cycle is completed before the upper clutch disengages and stops the upper drive. The Run In Key is usually pressed when there is a card in position 1 (i.e. in the Hopper) but no card in positions 2 and 3. In this case, two feeding cycles take place, bringing the card from position 1 to position 3, and the Q relay comes on. This action is modified by the presence originally of a card in position 2 or in position 3; in the former case there is only one feeding cycle before relay Q comes on; in the latter case, no feeding cycles at all, merely the stimulation of relay Q if it were previously off. Pressing the Run Out Key is effective only if the upper drive is stationary. In this case it initiates a sequence of feeding cycles which continue until position 3 is empty. If there were previously cards in the Hopper and positions 2 and 3, this has the effect of running them all out into the Stacker, since the lower drive always does two cycles on its own after the upper drive has stopped. The Initial Input Key is used for reading in a new program from scratch. It has three immediate effects; it sends two signals to the DEUCE which respectively clear the whole Delay Line store and stimulate NS-y-37/11-57

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Trigger READ and it also imitates the action of the Run In Key. Trigger READ is cleared immediately by any hole punched in column 54 which passes the Reading Brushes during a Reading Cycle. The Single-Shot Signal for this row occurs, but no subsequent ones. THE PUNCH The action of the Punch is very similar to that of the Reader. It will be described largely by references to the differences between the two. The most obvious difference is that, in place of the Reading Brushes, there are the Punching Knives, controlled by a set of Punch Magnets. On starting a sequence of Punching Cycles, the Destination 29 connections to the row of 32 OS lamps on the Control Panel are switched so as to operate also on 32 of these Punching Magnets. As each row of a card comes into position under the knives, there is punched on it the configuration at that time set up on the OS. After each row, a signal is sent from the Punch which clears the 0S. This saves the need to clear the OS by an instruction before setting up the configuration for each successive row; to cope with the first row of a sequence of cards, calling punch by the instruction "10-24" is also arranged to clear the OS. These remarks apply only to Punching Cycles; as in the case of the Reader, Feeding Cycles may take place in which there is no connection with the rest of the DEUCE. In the Punch, there is only one internal card position before the Punching Knives. This gives 5 card positions altogether, position 1 being the first card in the Hopper, position 2 coming before the Punching Knives, positions 3 and 4 afterwards, and position 5 being the last card in the Stacker. When a set of punching is complete, the last card punched remains in position 3. A Run Out Key is therefore provided which causes two Feeding Cycles and brings this card out into the Stacker. There is also a Run In Key (which in this case need never give more than one Feed- ing Cycle) and a separate Stop Key. Although there are three separate drives in the Punch connected together with clutches, this need not concern us at the moment; all the cards in the Punch always move at the same time. There is no question, for instance, of the cards in positions 1 and 2 standing still while the others move. As well as the 32 columns of information from the DEUCE, twelve more columns of reference numbers are also punched on each card. An eight- digit group of fixed parameters is punched on columns 5 to 12; those are set up on eight rotary switches before the start of the run. A four-digit card number is punched on columns 13 to 16, this card number steps on by one automatically for each card. The card number to be punched on the first card of the run is set up on a set of four rotary switches. NS-y-37/11-57