1. Interface

Mode	Size	Bank	RAM	Registers
20H	2Mbit ~ 16Mbit	00H ~ 3FH	6000H ~ 6BFFH	7F40H ~ 7FAFH

2. Technical Reference

2.1 Features

Developer	Capcom Co., Ltd.
Model	CX4 DL-2427
Processor	Hitachi HG51B169
Program ROM	32 K x 256 Words
Data ROM	1024 x 24-Bits
Stack	Circular, 8 x 23-Bits
Internal RAM	4 x 384 x 16-Bits
Clock	20MHz

2.1.1 Processor

Hitachi signed an agreement in 1991 with Compass Design Automation of the USA to work together to develop ASIC cell libraries based on 0.8 micron
CMOS processors. Hitachi launched in mid-1992 a 0.8 micron series of CMOS cell-based chips, designated the HG51B series.

Product	Technology	Line Width	Wiring Layers	Complex Cells	Propagation Delay (ns)	Power (mW)	Second Source
HG51B Series	CMOS	0.8μ	2 Metal	RAM, ROM, Datapath, Multiplier, Logic Synthesis	0.33	1.3μW/gate/Mhz	VLSI
Gate Count	Number of I/O	Voltage	Pin Count
300,000+	400+	5.0	QFP-80

2.2 Registers and Flags

Arithmetic and logic commands are performed on the Accumulator. Flags are set as the result of operation and are modified specific to each command.
The Accumulator is 24-bits wide.

Table 1: Base Registers

Symbol	Meaning	Reset Value
A	Accumulator	FFFFFF
Z	Zero Flag	0
N	Negative Flag	0
T	Greater Than Flag	0
V	Overflow Flag	0

2.2.1 General and Special Purpose Registers

General and Special Purpose Registers are accessible via a 7-bit register address space. This address space is available to all arithmetic and logic operations.
Transfer to the Accumulator is possible for all registers. All unmatched register addresses read zero (0).

Table 2: General Purpose Registers (GPR)

#	Symbol	Meaning	Bits	RW
60	R0	General Purpose Register	24	RW
61	R1	General Purpose Register	24	RW
62	R2	General Purpose Register	24	RW
63	R3	General Purpose Register	24	RW
64	R4	General Purpose Register	24	RW
65	R5	General Purpose Register	24	RW
66	R6	General Purpose Register	24	RW
67	R7	General Purpose Register	24	RW
68	R8	General Purpose Register	24	RW
69	R9	General Purpose Register	24	RW
6A	R10	General Purpose Register	24	RW
6B	R11	General Purpose Register	24	RW
6C	R12	General Purpose Register	24	RW
6D	R13	General Purpose Register	24	RW
6E	R14	General Purpose Register	24	RW
6F	R15	General Purpose Register	24	RW

Note: Register address space 60-6F is repeated through 70-7F.

Table 3: Special Purpose Registers (SPR)

#	Symbol	Meaning	Bits	RW	Reset Value
01	MACH	Multiply Accumulator	24	R	000000
02	MACL	Multiply Accumulator	24	R	000000
03	MBR	Memory Buffer Register	8*	RW	00
08	ROMB	Immediate ROM	24	R	DATA_ROM[0]
0C	RAMB	RAM Buffer	24	RW	000000
13	MAR	Memory Address Register	24	RW	FFFFFF
1C	DPR	RAM Address	12*	RW	000
20	IP	Instruction Pointer	8*	RW	00
28	P	Page Select	15*	RW	00FF
50	IR0	Immediate Register	24	R	000000
51	IR1	Immediate Register	24	R	FFFFFF
52	IR2	Immediate Register	24	R	00FF00
53	IR3	Immediate Register	24	R	FF0000
54	IR4	Immediate Register	24	R	00FFFF
55	IR5	Immediate Register	24	R	FFFF00
56	IR6	Immediate Register	24	R	800000
57	IR7	Immediate Register	24	R	7FFFFF
58	IR8	Immediate Register	24	R	008000
59	IR9	Immediate Register	24	R	007FFF
5A	IR10	Immediate Register	24	R	FF7FFF
5B	IR11	Immediate Register	24	R	FFFF7F
5C	IR12	Immediate Register	24	R	010000
5D	IR13	Immediate Register	24	R	FEFFFF
5E	IR14	Immediate Register	24	R	000100
5F	IR15	Immediate Register	24	R	00FEFF

* Registers less than 24 bits are zero extended.

Direct transfer from General Purpose Register to Special Purpose Register is also available for MBR, MAR and P.

2.3 Operands

The lower bits of the Instruction Register (IR) make up the operand.

Table 4: List of Operands

Symbol	Meaning	Bits
reg	Register Address	7
imm	Immediate	5/8
abs	Absolute	10
Rx	General Purpose Register	4

2.4 Instruction Set

IR	MSB	Mnemonic	Operand	Description		Modified
000000.. ........	00	NOP		No Operation
000010F. xxxxxxxx	08	BRA	imm	Branch (Always)
000011F. xxxxxxxx	0C	BEQ	imm	Branch on Equal (Z=1)
000100F. xxxxxxxx	10	BGE	imm	Branch on Greater or Equal (T=1)
000101F. xxxxxxxx	14	BMI	imm	Branch on Minus (N=1)
000110F. xxxxxxxx	18	BVS	imm	Branch on Overflow (V=1)
00100100 .......0	24	SKIPVC		Skip if No Overflow (V=0)
00100100 .......1	24	SKIPVS		Skip if Overflow (V=1)
00100101 .......0	25	SKIPLT		Skip if Less Than (T=0)
00100101 .......1	25	SKIPGE		Skip if Greater or Equal (T=1)
00100110 .......0	26	SKIPNE		Skip if Not Equal (Z=0)
00100110 .......1	26	SKIPEQ		Skip if Equal (Z=1)
00100111 .......0	27	SKIPPL		Skip if Plus (N=0)
00100111 .......1	27	SKIPMI		Skip if Minus (N=1)
001010F. xxxxxxxx	28	BSR	imm	Branch Subroutine
001011F. xxxxxxxx	2C	BSREQ	imm	Branch Subroutine on Equal (Z=1)
001100F. xxxxxxxx	30	BSRGE	imm	Branch Subroutine on Greater or Equal (T=1)
001101F. xxxxxxxx	34	BSRMI	imm	Branch Subroutine on Minus (N=1)
001110F. xxxxxxxx	38	BSRVS	imm	Branch Subroutine on Overflow (V=1)
001111.. ........	3C	RTS		Return from Subroutine
010000.. ........	40	RDBUS		Read External Memory Address	MBR = [MAR++]
010010SS .xxxxxxx	48	CMPR	A, reg	Comparison (Reverse)	R = reg - A	N Z T V
010011SS xxxxxxxx	4C	CMPR	A, imm	Comparison (Reverse)	R = imm - A	N Z T V
010100SS .xxxxxxx	50	CMP	A, reg	Comparison	R = A - reg	N Z T V
010101SS xxxxxxxx	54	CMP	A, imm	Comparison	R = A - imm	N Z T V
01011001 ........	59	EXTS	A	Sign Extension (8 bits)		N Z
01011010 ........	5A	EXTS	A	Sign Extension (16 bits)		N Z
01100000 .xxxxxxx	60	MOV	A, reg	Data Transfer Instruction	A = reg
01100001 .xxxxxxx	61	MOV	MBR, reg**	Data Transfer Instruction	MBR = reg**
01100010 ....xxxx	62	MOV	MAR, Rx	Data Transfer Instruction	MAR = Rx
01100011 ....xxxx	63	MOV	P, Rx	Data Transfer Instruction	P = Rx
01100100 xxxxxxxx	64	MOV	A, imm	Data Transfer Instruction	A = imm
01100101 xxxxxxxx	65	MOV	MBR, imm	Data Transfer Instruction	MBR = imm
01100110 xxxxxxxx	66	MOV	MAR, imm	Data Transfer Instruction	MAR = imm
01100111 xxxxxxxx	67	MOV	P, imm	Data Transfer Instruction	P = imm
01101000 ........	68	RDRAM	0, A	Read Data RAM	RAMB[0] = DATA_RAM[A]
01101001 ........	69	RDRAM	1, A	Read Data RAM	RAMB[1] = DATA_RAM[A]
01101010 ........	6A	RDRAM	2, A	Read Data RAM	RAMB[2] = DATA_RAM[A]
01101100 xxxxxxxx	6C	RDRAM	0, imm	Read Data RAM	RAMB[0] = DATA_RAM[DPR + imm]
01101101 xxxxxxxx	6D	RDRAM	1, imm	Read Data RAM	RAMB[1] = DATA_RAM[DPR + imm]
01101110 xxxxxxxx	6E	RDRAM	2, imm	Read Data RAM	RAMB[2] = DATA_RAM[DPR + imm]
011100.. ........	70	RDROM	A	Read Data ROM	ROMB = DATA_ROM[A]
011101xx xxxxxxxx	74	RDROM	abs	Read Data ROM	ROMB = DATA_ROM[abs]
01111100 xxxxxxxx	7C	MOV	PL, imm	Data Transfer Instruction	P[0] = imm
01111101 .xxxxxxx	7D	MOV	PH, imm	Data Transfer Instruction	P[1] = imm
100000SS .xxxxxxx	80	ADD	A, reg	Binary Addition	A = A + reg	N Z T V
100001SS xxxxxxxx	84	ADD	A, imm	Binary Addition	A = A + imm	N Z T V
100010SS .xxxxxxx	88	SUBR	A, reg	Binary Subtraction (Reverse)	A = reg - A	N Z T V
100011SS xxxxxxxx	8C	SUBR	A, imm	Binary Subtraction (Reverse)	A = imm - A	N Z T V
100100SS .xxxxxxx	90	SUB	A, reg	Binary Subtraction	A = A - reg	N Z T V
100101SS xxxxxxxx	94	SUB	A, imm	Binary Subtraction	A = A - imm	N Z T V
100110.. .xxxxxxx	98	MUL	reg	Signed Multiplication	MACH:MACL = A * reg
100111.. xxxxxxxx	9C	MUL	imm	Signed Multiplication	MACH:MACL = A * imm
101000SS .xxxxxxx	A0	XNOR	A, reg	Inverse Exclusive OR	A = A ^ !reg	N Z
101001SS xxxxxxxx	A4	XNOR	A, imm	Inverse Exclusive OR	A = A ^ !imm	N Z
101010SS .xxxxxxx	A8	XOR	A, reg	Exclusive OR	A = A ^ reg	N Z
101011SS xxxxxxxx	AC	XOR	A, imm	Exclusive OR	A = A ^ imm	N Z
101100SS .xxxxxxx	B0	AND	A, reg	Logical AND	A = A & reg	N Z
101101SS xxxxxxxx	B4	AND	A, imm	Logical AND	A = A & imm	N Z
101110SS .xxxxxxx	B8	OR	A, reg	Logical OR	A = A \| reg	N Z
101111SS xxxxxxxx	BC	OR	A, imm	Logical OR	A = A \| imm	N Z
110000.. .xxxxxxx	C0	SHLR	A, reg	Shift Logical Right	A = unsigned(A) >> reg	N Z
110001.. ...xxxxx	C4	SHLR	A, imm	Shift Logical Right	A = unsigned(A) >> imm	N Z
110010.. .xxxxxxx	C8	SHAR	A, reg	Shift Arithmetic Right	A = signed(A) >> reg	N Z
110011.. ...xxxxx	CC	SHAR	A, imm	Shift Arithmetic Right	A = signed(A) >> imm	N Z
110100.. .xxxxxxx	D0	ROTR	A, reg	Rotate Right		N Z
110101.. ...xxxxx	D4	ROTR	A, imm	Rotate Right		N Z
110110.. .xxxxxxx	D8	SHLL	A, reg	Shift Logical center	A = A << reg	N Z
110111.. ...xxxxx	DC	SHLL	A, imm	Shift Logical center	A = A << imm	N Z
11100000 .xxxxxxx	E0	MOV	reg, A	Data Transfer Instruction	reg = A
11100001 .xxxxxxx	E1	MOV	reg**, MBR	Data Transfer Instruction	reg** = MBR
11101000 ........	E8	WRRAM	0, A	Write Data RAM	DATA_RAM[A] = RAMB[0]
11101001 ........	E9	WRRAM	1, A	Write Data RAM	DATA_RAM[A] = RAMB[1]
11101010 ........	EA	WRRAM	2, A	Write Data RAM	DATA_RAM[A] = RAMB[2]
11101100 xxxxxxxx	EC	WRRAM	0, imm	Write Data RAM	DATA_RAM[DPR + imm] = RAMB[0]
11101101 xxxxxxxx	ED	WRRAM	1, imm	Write Data RAM	DATA_RAM[DPR + imm] = RAMB[1]
11101110 xxxxxxxx	EE	WRRAM	2, imm	Write Data RAM	DATA_RAM[DPR + imm] = RAMB[2]
111100.. ....xxxx	F0	SWAP	A, Rx	Data Transfer Instruction	tmp = A; A = Rx; Rx = tmp
111110.. ........	F8	CLEAR		Data Transfer Instruction	A = DPR = P = RAMB = 0
111111.. ........	FC	HALT		Halt Operation

** Registers 60-7F only.

2.5 Notes

1. Branch instructions are either near or far.
2. Arithmetic and logic commands shift the value of the Accumulator 0, 1, 8, or 16 bits before operation.
3. The shift counter is 5 bits. A count larger than twenty four (24) is replaced with zero (0).
4. Unable to test RDBUS on a Mash-mods Flash Programmer.