CX4 Gamepaks

Mega Man X 2 Mega Man X 3

Mega Man X 2 (a.k.a. Rockman X 2)
Mega Man X 3 (a.k.a. Rockman X 3)

1. Interface

Mode Size Bank RAM Registers
20H 2Mbit ~ 16Mbit 00H ~ 3FH 6000H ~ 6BFFH 7F40H ~ 7FAFH

2. Technical Reference

2.1 Features

DeveloperCapcom Co., Ltd.
ModelCX4 DL-2427
ProcessorHitachi HG51B169
Program ROM32 K x 256 Words
Data ROM1024 x 24-Bits
StackCircular, 8 x 23-Bits
Internal RAM4 x 384 x 16-Bits
Clock20MHz

2.2 Registers

Arithmetic and logic commands are performed on the Accumulator. Flags are set as the result of operation
and are modified specific to each command. The Accumulator is 24-bits wide.

Table 1: Base Registers
SymbolMeaningReset Value
AAccumulatorFFFFFF
ZZero Flag0
NNegative Flag0
TGreater Than Flag0
VOverflow Flag0

2.2.1 General and Special Purpose Registers

General and Special Purpose Registers are accessible via a 7-bit register address space. This address
space is available to all arithmetic and logic operations. Transfer to the Accumulator is possible for all
registers. All unmatched register addresses read zero (0).

Table 2: General Purpose Registers (GPR)
#SymbolMeaningBitsRWReset Value
60R0General Purpose Register24RW000000
61R1General Purpose Register24RW000000
62R2General Purpose Register24RW000000
63R3General Purpose Register24RW000000
64R4General Purpose Register24RW000000
65R5General Purpose Register24RW000000
66R6General Purpose Register24RW000000
67R7General Purpose Register24RW000000
68R8General Purpose Register24RW000000
69R9General Purpose Register24RW000000
6AR10General Purpose Register24RW000000
6BR11General Purpose Register24RW000000
6CR12General Purpose Register24RW000000
6DR13General Purpose Register24RW000000
6ER14General Purpose Register24RW000000
6FR15General Purpose Register24RW000000
Note: Register address space 60-6F is repeated through 70-7F.

Table 3: Special Purpose Registers (SPR)
#SymbolMeaningBitsRWReset Value
01MACHMultiply Accumulator24R000000
02MACLMultiply Accumulator24R000000
03MBRMemory Buffer Register8*RW00
13MARMemory Address Register24RWFFFFFF
08ROMBImmediate ROM24RDATA_ROM[0]
0CRAMBRAM Buffer24RW000000
1CDPRRAM Address12*RW000
20IPInstruction Pointer8*RW00
28PPage Select15*RW00FF
50IR0Immediate Register24R000000
51IR1Immediate Register24RFFFFFF
52IR2Immediate Register24R00FF00
53IR3Immediate Register24RFF0000
54IR4Immediate Register24R00FFFF
55IR5Immediate Register24RFFFF00
56IR6Immediate Register24R800000
57IR7Immediate Register24R7FFFFF
58IR8Immediate Register24R008000
59IR9Immediate Register24R007FFF
5AIR10Immediate Register24RFF7FFF
5BIR11Immediate Register24RFFFF7F
5CIR12Immediate Register24R010000
5DIR13Immediate Register24RFEFFFF
5EIR14Immediate Register24R000100
5FIR15Immediate Register24R00FEFF
* Registers less than 24 bits are zero extended.

Direct transfer from General Purpose Register to Special Purpose Register is also available for MBR, MAR and P.

2.3 Operands

The lower bits of the Instruction Register (IR) make up the operand.

Table 4: List of Operands
SymbolMeaningBits
regRegister Address7
immImmediate5/8
absAbsolute10
RxGeneral Purpose Register4

2.4 Instruction Set

IRMSBMnemonicOperandDescriptionModified
000000.. ........00NOPNo Operation
000010F. xxxxxxxx08BRAimmBranch (Always)
000011F. xxxxxxxx0CBEQimmBranch on Equal (Z=1)
000100F. xxxxxxxx10BGEimmBranch on Greater or Equal (T=1)
000101F. xxxxxxxx14BMIimmBranch on Minus (N=1)
000110F. xxxxxxxx18BVSimmBranch on Overflow (V=1)
00100100 .......024SKIPVCSkip if No Overflow (V=0)
00100100 .......124SKIPVSSkip if Overflow (V=1)
00100101 .......025SKIPLTSkip if Less Than (T=0)
00100101 .......125SKIPGESkip if Greater or Equal (T=1)
00100110 .......026SKIPNESkip if Not Equal (Z=0)
00100110 .......126SKIPEQSkip if Equal (Z=1)
00100111 .......027SKIPPLSkip if Plus (N=0)
00100111 .......127SKIPMISkip if Minus (N=1)
001010F. xxxxxxxx28BSRimmBranch Subroutine
001011F. xxxxxxxx2CBSREQimmBranch Subroutine on Equal (Z=1)
001100F. xxxxxxxx30BSRGEimmBranch Subroutine on Greater or Equal (T=1)
001101F. xxxxxxxx34BSRMIimmBranch Subroutine on Minus (N=1)
001110F. xxxxxxxx38BSRVSimmBranch Subroutine on Overflow (V=1)
001111.. ........3CRTSReturn from Subroutine
010000.. ........40RDBUSRead External Memory AddressMBR = [MAR++]
010010SS .xxxxxxx48CMPRA, regComparison (Reverse)R = reg - AN Z T V
010011SS xxxxxxxx4CCMPRA, immComparison (Reverse)R = imm - AN Z T V
010100SS .xxxxxxx50CMPA, regComparisonR = A - regN Z T V
010101SS xxxxxxxx54CMPA, immComparisonR = A - immN Z T V
01011001 ........59EXTSASign Extension (8 bits)N Z
01011010 ........5AEXTSASign Extension (16 bits)N Z
01100000 .xxxxxxx60MOVA, regData Transfer InstructionA = reg
01100001 .xxxxxxx61MOVMBR, reg**Data Transfer InstructionMBR = reg**
01100010 ....xxxx62MOVMAR, RxData Transfer InstructionMAR = Rx
01100011 ....xxxx63MOVP, RxData Transfer InstructionP = Rx
01100100 xxxxxxxx64MOVA, immData Transfer InstructionA = imm
01100101 xxxxxxxx65MOVMBR, immData Transfer InstructionMBR = imm
01100110 xxxxxxxx66MOVMAR, immData Transfer InstructionMAR = imm
01100111 xxxxxxxx67MOVP, immData Transfer InstructionP = imm
01101000 ........68RDRAM0, ARead Data RAMRAMB[0] = DATA_RAM[A]
01101001 ........69RDRAM1, ARead Data RAMRAMB[1] = DATA_RAM[A]
01101010 ........6ARDRAM2, ARead Data RAMRAMB[2] = DATA_RAM[A]
01101100 xxxxxxxx6CRDRAM0, immRead Data RAMRAMB[0] = DATA_RAM[DPR + imm]
01101101 xxxxxxxx6DRDRAM1, immRead Data RAMRAMB[1] = DATA_RAM[DPR + imm]
01101110 xxxxxxxx6ERDRAM2, immRead Data RAMRAMB[2] = DATA_RAM[DPR + imm]
011100.. ........70RDROMARead Data ROMROMB = DATA_ROM[A]
011101xx xxxxxxxx74RDROMabsRead Data ROMROMB = DATA_ROM[abs]
01111100 xxxxxxxx7CMOVPL, immData Transfer InstructionP[0] = imm
01111101 .xxxxxxx7DMOVPH, immData Transfer InstructionP[1] = imm
100000SS .xxxxxxx80ADDA, regBinary AdditionA = A + regN Z T V
100001SS xxxxxxxx84ADDA, immBinary AdditionA = A + immN Z T V
100010SS .xxxxxxx88SUBRA, regBinary Subtraction (Reverse)A = reg - AN Z T V
100011SS xxxxxxxx8CSUBRA, immBinary Subtraction (Reverse)A = imm - AN Z T V
100100SS .xxxxxxx90SUBA, regBinary SubtractionA = A - regN Z T V
100101SS xxxxxxxx94SUBA, immBinary SubtractionA = A - immN Z T V
100110.. .xxxxxxx98MULregSigned MultiplicationMACH:MACL = A * reg
100111.. xxxxxxxx9CMULimmSigned MultiplicationMACH:MACL = A * imm
101000SS .xxxxxxxA0XNORA, regInverse Exclusive ORA = A ^ !regN Z
101001SS xxxxxxxxA4XNORA, immInverse Exclusive ORA = A ^ !immN Z
101010SS .xxxxxxxA8XORA, regExclusive ORA = A ^ regN Z
101011SS xxxxxxxxACXORA, immExclusive ORA = A ^ immN Z
101100SS .xxxxxxxB0ANDA, regLogical ANDA = A & regN Z
101101SS xxxxxxxxB4ANDA, immLogical ANDA = A & immN Z
101110SS .xxxxxxxB8ORA, regLogical ORA = A | regN Z
101111SS xxxxxxxxBCORA, immLogical ORA = A | immN Z
110000.. .xxxxxxxC0SHLRA, regShift Logical RightA = unsigned(A) >> regN Z
110001.. ...xxxxxC4SHLRA, immShift Logical RightA = unsigned(A) >> immN Z
110010.. .xxxxxxxC8SHARA, regShift Arithmetic RightA = signed(A) >> regN Z
110011.. ...xxxxxCCSHARA, immShift Arithmetic RightA = signed(A) >> immN Z
110100.. .xxxxxxxD0ROTRA, regRotate RightN Z
110101.. ...xxxxxD4ROTRA, immRotate RightN Z
110110.. .xxxxxxxD8SHLLA, regShift Logical LeftA = A << regN Z
110111.. ...xxxxxDCSHLLA, immShift Logical LeftA = A << immN Z
11100000 .xxxxxxxE0MOVreg, AData Transfer Instructionreg = A
11100001 .xxxxxxxE1MOVreg**, MBRData Transfer Instructionreg** = MBR
11101000 ........E8WRRAM0, AWrite Data RAMDATA_RAM[A] = RAMB[0]
11101001 ........E9WRRAM1, AWrite Data RAMDATA_RAM[A] = RAMB[1]
11101010 ........EAWRRAM2, AWrite Data RAMDATA_RAM[A] = RAMB[2]
11101100 xxxxxxxxECWRRAM0, immWrite Data RAMDATA_RAM[DPR + imm] = RAMB[0]
11101101 xxxxxxxxEDWRRAM1, immWrite Data RAMDATA_RAM[DPR + imm] = RAMB[1]
11101110 xxxxxxxxEEWRRAM2, immWrite Data RAMDATA_RAM[DPR + imm] = RAMB[2]
111100.. ....xxxxF0SWAPA, RxData Transfer Instructiontmp = A; A = Rx; Rx = tmp
111110.. ........F8CLEARData Transfer InstructionA = DPR = P = RAMB = 0
111111.. ........FCHALTHalt Operation

** Registers 60-7F only.

2.5 Notes

1. Branch instructions are either near or far.
2. Arithmetic and logic commands shift the value of the Accumulator left 0, 1, 8, or 16 bits before operation.
3. The shift counter is 5 bits. A count larger than twenty four (24) is replaced with zero (0).
4. Unable to test RDBUS on a Mash-mods Flash Programmer.




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